OR3TP12 datasheet(28/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

Symbol

I/O

Description

Clock

Domain

Miscellaneous Signals (continued)

cfgshiftenn

pci_cfg_stat

PCI Error Status Control

cfgshiftenn is an active-low signal that MUXes the output of the PCI device

status register (PCI Specification 2.1: Section 6.2.3) onto signal

pci_cfg_stat:

cfgshiftenn = 1:

pci_cfg_stat outputs the wired-OR of all status bits

below, after being masked by options in the FPSC

configuration manager.

cfgshiftenn = 0:

pci_cfg_stat outputs each status bit below, shifted

one at a time on successive pciclk rising edges.

The shift register is reset when cfgshiftenn = 1.

Device Status Register bits:

Detected Parity Error, Signaled System Error,

Received Master Abort, Received Target Abort,

Signaled Target Abort, Master Data Parity Error.

pciclk

pci_64bit

PCI 64-Bit Bus Indication. This active-high signal indicates that the embed-

ded core detected that it is configured as a 64-bit agent on the PCI bus. This

is the result of detecting PCI signal req64n as active-low on the rising edge

of PCI signal rstn. Note that this does not imply that any particular transac-

tion is 64-bit, since each transaction is individually negotiated using PCI sig-

nals req64n and ack64n. When asserted, all data transfers across the

Master and Target FIFO interface will imply 64-bit data phases.

—

fifo_sel

FIFO Select. A MUX control signal that is valid in the dual-port mode to

select either Master read data (fifo_sel = 0) or Target address/write data

(fifo_sel = 1) on the datatofpga and datatofpgax bus. For quad-port mode,

this signal can be tied to high.

—

PCI Bus Core Detailed Description (continued)

Table 6. Embedded Core/FPGA Interface Signals (continued)

* The source of the clock (fclk1 or fclk2) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.

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