OR3TP12 datasheet(16/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

PCI Protocol Fundamentals

Basic Transfer Control

The following paragraphs describe various aspects of

the PCI protocol and the way they are handled by the

PCI bus core.

Addressing. The PCI Specification defines three types

of address spaces. The first, configuration address

space, is a physical address space that is intended as

a means for powerup software to identify agents and

allocate them address space. The second, I/O address

space, is intended for mapping I/O control functions.

The third, memory address spaces, is intended for bulk

data transfer. It has features to facilitate this, such as

special commands for cache implementation, large

page sizes, and mechanisms for prefetching. The PCI

bus core handles all three address space types as both

a Master and a Target.

Byte Alignment. On all write operations (configuration,

I/O, and memory) for both the PCI bus core’s Master

and Target functions, byte enables are fully imple-

mented from/to the FPGA interface. Note, however,

that even though the PCI bus core implements the abil-

ity to control byte enables for the memory write and

invalidate instruction, the PCI Specification requires

that this instruction assert all byte enables, and this is

the FPGA application’s responsibility. On read opera-

tions, the utility of byte enables is more dubious since

the data must be enroute from the PCI bus Target to

Master, at the time that the corresponding byte enables

are enroute from the PCI bus Master to Target (unless

wait-states are inserted). The PCI bus core, therefore,

does not implement full-byte enable control for Target

reads, and limited for Master reads.

For the OR3TP12, byte enables on Master read burst

operations must always be asserted; nonburst Master

reads may manipulate the byte enables. Byte enables

on Target read operations are ignored, in accordance

with PCI Specification 2.1, Section 3.2.3. All Master

burst read and write addresses must be aligned on

64-bit boundaries. Single read and write addresses can

be aligned on 32-bit boundaries.

Device Selection (devseln)

The Target is responsible for decoding the address of a

aster’s request by asserting the PCI bus signal

devseln. devseln may be asserted one, two, or three

clocks after the address phrase of a transaction, corre-

sponding to fast, medium, or slow decode, respectively.

The PCI bus core’s Target is capable of performing a

medium-speed decode response. The decode

response speed has a significant impact on the overall

latency and bandwidth of nonburst PCI transactions. Its

impact decreases greatly for burst transactions, partic-

ularly for burst lengths of the size of the PCI bus core’s

FIFOs.

Address/Data Stepping

Stepping is an optional feature added to the PCI Speci-

fication to accommodate agents whose bus drive capa-

bility is insufficient to handle large groups of signals

changing state in one clock cycle. Continuous stepping

allows weak drivers multiple cycles for signal transition.

Discrete stepping partitions the bus into two or more

groups of bits that transition on successive clock

cycles. However, stepping exacts a heavy toll on perfor-

mance, cutting maximum bandwidth by at least 50%

and increasing latency. The PCI core is designed for

maximum throughput with high-performance buffers, so

stepping is unnecessary and not implemented. The

wait cycle control, bit seven of the command register, is

therefore hardwired to a 0.

Interrupt Acknowledge

The interrupt acknowledge command is a read by the

system CPU implicitly addressed to the system inter-

rupt controller. Other agents, including the PCI bus

core, are not required to implement this instruction; the

PCI bus core’s Master does not generate it, and its Tar-

get ignores it.

Arbitration Parking

The PCI Specification requires that all Master agents

properly handle bus parking, which means that when

that agent receives an asserted gntn without the agent

having asserted its reqn, the agent still must drive sig-

nal par and buses ad and c_ben to a stable value. The

PCI bus core meets this requirement.

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