OR3TP12 datasheet(46/128 Pages) AGERE

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Lucent Technologies Inc.

ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Master Controller

Detailed Description (continued)

To enter the dual-port data phase, maenn is deas-

serted, mrdataenn is asserted, fifo_sel is deasserted,

and a valid 32-bit word of data will be provided on bus

datatofpga, providing the read data FIFO is not empty

(mr_emptyn = 1). For a 32-bit transfer on a

32-bit PCI bus (pci_64bit = 0), the Master FIFO inter-

face will assert the signal mrlastcycn during the only

clock of the data phase. The completion of the data

phase is indicated by mrlastcycn being asserted,

requiring mrdataenn asserted, and the final data word.

For quad-port mode (Figure 10), the command/address

phase starts with the command and read burst length

transferring on the bus mwdata in sequential 18-bit

segments. The 18-bit Master command will be trans-

ferred first on mwdata, followed the 18-bit read burst

length, with both validated by an asserted maenn. The

32-bit address will be split into two 16-bit components

with the LSB being transferred first, also validated by

an asserted maenn. The command/address phase will

require four clock cycles, and mwlastcycn will be

asserted on the final or MSB component of the

address.

In the data phase of the quad-port mode, the read data

will be transferred in 16-bit segments on bus mrdata.

The read data phase will require two clock cycles to

transfer the 32-bit read data word across the 16-bit bus

mrdata, providing mrdataen is asserted, and the read

data FIFOs are not empty (mr_emptyn = 1). mrlast-

cycn will be deasserted for the first 16-bit LSB of the

read data word, and asserted for the final 16-bit MSB

component.

Following this command/address setup, execution

begins on the PCI bus. Figure 11 shows the timing of a

typical transaction with a remote Target. The transac-

tion results in a normal completion. The remote Target

supports fast decode, and the protocol and timing are

as required by the PCI Specification.

5-7352(F)

Figure 9. Master Read Single (FIFO Interface, Dual-Port)

TN+1

TN+2

TN+3

BRST/CMD

ADRS

DATA

fclk

m_ready

mstatecntr

ma_fulln

datafmfpga

maenn

mwlastcycn

datatofpga

fifo_sel

mr_emptyn

mrdataenn

mrlastcycn

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