OR3TP12 datasheet(55/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed Description (continued)

For a write burst transaction to an odd address (ad2 = 1), the first write data word transferred to the FPGA applica-

tion will have all its byte enables deasserted and can be discarded. For Target read transactions to an odd address

(ad2 = 1), the first read data word provided by the FPGA application is discarded by the Target FIFO interface.

For single transaction (burst indication bit deasserted) on 32-bit PCI bus (pci_64bit = 0), the Target FIFO interface

handles all data alignment. The received address is valid as transferred, with the data phase aligning to this

address. No extra data is transferred or discarded.

Table 19. Target State Counter (TStateCntr) Values and the Corresponding Bus Data

TStateCntr[3:0]

Dual-Port Mode (32-bit Ports)

Quad-Port Mode (16-bit Ports)

Data on Bus

datatofpga

Data on Bus

datafmfpga

Data on Bus

twdata

Data on Bus

trdata

Adrs[31:0]

Data[31:0]

Adrs[15:0]

Data[15:0]

Adrs[63:32]

Data[63:32]

Adrs[31:16]

Data[31:16]

—

Adrs[47:32]

Data[47:32]

—

Adrs[63:48]

Data[63:48]

Data[31:0]

—

Data[15:0]

—

Data[63:32]

—

Data[31:16]

—

Data[47:32]

—

Data[63:48]

—

8—

—

9—

—

A—

—

B—

—

C—

—

D—

—

E—

—

F—

—

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