OR3TP12 datasheet(32/128 Pages) AGERE

32 / 128 page

ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

Subsystem Vendor ID

0x2C—0x2D

Any 16-bit value.

Subsystem ID

0x2E—0x2F

Any 16-bit value.

Minimum Grant (Min_Gnt)

0x3E

Any 8-bit value.

Maximum Latency (Max_Lat)

0x3F

Any 8-bit value.

Port Mode

Dual-port or quad-port.

I/O Mode

Fast or slew-limited PCI output buffers.

Master FIFO Interface Clock

fclk1 or fclk2.

Target FIFO Interface Clock

fclk1 or fclk2.

Target Address Comparator

Enabled or disabled; when enabled, the Target FIFO

interface will not transfer the MSB of the Target

address to the FPGA application, if it matches the

value of the previous transferred address. For dual-

port, the MSB will cover bits [64:32], whereas for

quad-port, the MSB represents bits [64:17]. If dis-

abled, the FPGA application will receive the address

covering the decoded BAR space.

Target Maximum Initial Latency

Normal (16) or extended (32): The number of wait-

states to insert on Target reads until valid data is

recognized in the Target read data FIFOs. If no data

is detected, the Target will disconnect. Note that

only normal initial latency complies with PCI Specifi-

cation 2.2, Section 3.5.1.1. Extended latency may

be specified in proprietary systems where additional

clocks are required to return the first data word.

Description

Hex Address in PCI

Configuration

Space

Optional Settings

PCI Bus Core Detailed Description (continued)

Table 8. PCI Bus Core Options Settable via FPGA Configuration RAM Bits (continued)

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