OR3TP12 datasheet(35/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Master Controller Detailed Description (continued)

Table 10. Bit Definitions for Master Command/Address Phase

* Refer to PCI Specification 2.3 Section 3.1.

Master Write Operation

Command/Address Setup

In order to initiate a PCI Master write operation, the FPGA application must supply the Master command and PCI

start address in the specific order prescribed in Table 13 and Table 14, for quad- and dual-port mode respectively.

This data is transferred via bus mwdata (quad-port mode) or datafmfpga(x) (dual-port mode) and will be accepted

by the Master FIFO interface when ma_fulln is inactive and m_ready is active. The Master command word and

address must be accompanied by assertion of the enable maenn, with the command/address phase ending with

the assertion of mwlastcycn. The bit definitions of the Master command word is shown in Table 10. For Master

writes, the same burst length bit must be equal to zero.

All burst transactions or 64-bit agents (pci_64bit = 1) must start transactions on a 64-bit address boundary, which

requires address bit ad2 = 0 for the PCI start address. If the write transaction needs to start on a odd 32-bit

address boundary (ad2 = 1), the FPGA must send a padding data word to properly fill/align the Master write data

FIFO at the beginning of the data phase. This padding data word will be the first write data word transferred from

the FPGA application, and will have all of its byte enables deasserted. When the Master starts the PCI transaction

on a 32-bit bus, this padding data word will be dropped by the Master, with the resulting transaction starting on the

odd address (ad2 = 1).

For single 32-bit transaction on 32-bit buses (pci_64bit = 0), the Master FIFO interface will perform the proper data

alignment. The FPGA application will transfer the PCI starting address, even or odd, during the command/address

phase and the valid 32-bit data word during the data phase.

Bits

Name

Description

Quad-Port

Dual-Port

Master Command Word (FPGA

→ PCI Core)

SPL

Master Read: Same Previous Burst

Length Indication (quad-port only)

Master Write: Must Be Zero

mwdata[17]

datafmfpgax[3]

Dual-Address Indication

mwdata[16]

datafmfpgax[2]

15:13

—

Not Used

mwdata[15:13]

datafmfpga[31:29]

Holding Register Selector:

0 = Select HR0

1 = Select HR1

mwdata[12]

datafmfpga[28]

11:4

MRDBEN

Master Read: Byte Enables

Master Write: Not Used

mwdata[11:4]

datafmfpga[27:20]

3:0

Cmd

PCI Command Code*

mwdata[3:0]

datafmfpga[19:16]

Master Read Burst Length Word (FPGA

→ PCI Core)

17:16

Burst Length of 64-bit Words

mwdata[17:16]

datafmfpgax[1:0]

15:0

Burst Length of 64-bit Words

mwdata[15:0]

datafmfpga[15:0]

Master Address Word (FPGA

→ PCI Core)

17:16

—

Not Used

mwdata[17:16]

datafmfpgax[1:0]

15:0

Adrs

Address

mwdata[15:0]

datafmfpga[31:0]

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