OR3TP12 datasheet(21/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description (continued)

Embedded Core/FPGA Interface Signal Descriptions

In Table 6, an input refers to a signal flowing into the FPGA logic (out of the embedded core) and an output refers

to a signal flowing out of the FPGA logic (into the embedded core).

Table 6. Embedded Core/FPGA Interface Signals

Symbol

I/O

Description

Clock

Domain

Master General Signals

fpga_mbusyn

FPGA Master Is Busy. The FPGA application asserts this active-low signal to

indicate to the Master to assert the reqn signal until fpga_mbusyn becomes

inactive or the Target disconnects. This is helpful in PCI applications in which

Master has multiple high-priority transactions to be performed. Once asserted,

this signal needs to remain asserted for a minimum of two pciclk cycles.

pciclk

fpga_msyserror

FPGA Master Cycle Aborted by PCI Target. The Master controller asserts

this active-high signal as an indication that the current cycle to the PCI bus has

been aborted.

fclk*

mstatecntr[3:0]

Master State Counter. Indicates the current state of the Master FIFO inter-

face. Details of the Master FIFO interface can be found in the PCI Bus Core

Master Controller Detailed Description section of this data sheet.

fclk*

mfifoclrn

Master FIFO Clear. This active-low signal is asynchronously asserted by the

FPGA application to clear the Master address, read, and write FIFOs, along

with mstatecntr. This signal does not reset the Master Controllers PCI state

machine within the embedded core, and therefore it is not recommended to be

used to terminate the current PCI transaction.

—

m_ready

Master Logic Ready. This active-high signal indicates that the Master FIFO

interface to the FPGA logic is ready. This signal will be inactive during PCI bus

resets and Master FIFO clears.

fclk*

Master FIFO Address and Command Control Signals

maenn

Master Command/Start Address/Read Burst Length Enable. This is an ac-

tive-low signal used to register the Master command word, read burst length,

and PCI start address into the Master controller registers. The type of data

transferred from the FPGA application will depend on the current state of

mstatecntr and the interface mode (quad-port or dual-port). Further description

is provided in the Command/Address Setup section (see page 35) of the PCI

Bus Core Master Controller Detailed Description section.

fclk*

ma_fulln

Master Address Register Full Flag. This active-low signal indicates that the

Master address register is full and no new PCI Master transactions can be ac-

cepted from the FPGA application. This flag is cleared when the Master trans-

action is completed on the PCI bus. For Master writes, ma_fulln is cleared

when all write data has been transferred to the external Target. For Master

reads, ma_fulln is cleared when all read data has been received from the ex-

ternal Target, although all read data may not have been transferred to the FPGA

application.

fclk*

* The source of the clock (fclk1 or fclk2) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.

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