OR3TP12 datasheet(71/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed Description (continued)

Example: Target Read Memory, Single-Word, Delayed Transaction

Figure 26 shows the timing on the PCI bus interface for a Target single 32-bit memory read handled as a delayed

transaction (deltrn = 0). The timing on the PCI interface (Figure 26) is similar to that of a delayed I/O read

(Figure 24) except that stopn is not asserted here to cause disconnect with data.

5-7549(F)

Figure 26. Target Single Memory Read, Delayed (PCI Bus, 32-Bit)

The FPGA interface timing is as shown in Figure 27 and Figure 28 for dual- and quad-port respectively. The FPGA

interface timing is similar for all Target reads and is described below in the Single Target Read FIFO Interface sec-

tion.

TRANSACTION #1: ADDRESS, BYTE ENABLES,

AND COMMAND LATCHED AS A

DELAYED READ REQUEST.

TRANSACTION #2: DISCONNECTED WITHOUT DATA

BECAUSE READ OPERATION NOT COMPLETED.

TRANSACTION #3: DISCONNECTED WITH DATA

BECAUSE READ OPERATION COMPLETED.

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Tb0

Tb1

Tb2

Tb3

Tb4

Tb5

Tb6

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

ADRS

DATA

CMD

BEs

CMD BYTE ENABLES

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

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