OR3TP12 datasheet(43/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Master Controller Detailed Description (continued)

Table 13. Dual-Port Master Writes

1. When maenn and ma_fulln are deasserted high, the Master interface is idle.

2. When maenn is asserted low, a command/address phase is in progress.

3. maenn must be asserted low for command/address data to transfer and state to change.

4. maenn must be deasserted high and mwdataenn must be asserted low to execute the data phase and state to change.

5. Next state = 0 if mwlastcycn is asserted low (end of Master write data phase).

6. Next state = A if mwlastcycn is asserted low (end of Master command/address phase).

Table 14. Quad-Port Master Writes

1. When maenn and ma_fulln are deasserted high, the Master interface is idle.

2. When maenn is asserted low, a command/address phase is in progress.

3. maenn must be asserted low for command/address data to transfer and state to change.

4. maenn must be deasserted high and mwdataenn must be asserted low to execute the data phase and state to change.

5. Next state = 0 if mwlastcycn is asserted low (end of Master write data phase).

6. Next state = 6 if mwlastcycn is asserted low (end of Master command/address phase).

MStateCntr

Next State of

MStateCntr

Description

Data on Bus

datafmfpgax[3:0],

datafmfpga[31:0]

Notes

Idle

XXXX4, XXXX16

1 or A

Command Word

Command Word [17:16], XX2,

Command Word [15:0], XXXX16

2, 3, 6

2 or A

Address[31:0]

XXXX4, PCIAddress[31:0]

2, 3, 6

Address[63:32]

XXXX4, PCIAddress[63:32]

2, 3, 6

B or 0

Data[31:0]

BEN[3:0], PCIData[31:0]

4, 5

A or 0

Data[63:32]

BEN[7:4], PCIData[63:32]

4, 5

MStateCntr

Next State of

MStateCntr

Description

Data on Bus

mwdata[17:0]

Notes

Idle

XX2, XXXX16

1 or 6

Command Word

2, 3, 6

2 or 6

Address[15:0]

XX2, PCIAddress[15:0]

2, 3, 6

3 or 6

Address[31:16]

XX2, PCIAddress[31:16]

2, 3, 6

4 or 6

Address[47:32]

XX2, PCIAddress[47:32]

2, 3, 6

Address[63:48]

XX2, PCIAddress[63:48]

2, 3, 6

Data[15:0]

BEN[1:0], PCIData[15:0]

8 or 0

Data[31:16]

BEN[3:2], PCIData[31:16]

4, 5

Data[47:32]

BEN[5:4], PCIData[47:32]

6 or 0

Data[63:48]

BEN[7:6], PCIData[63:48]

4, 5

Master Read Operation

Command/Address Setup

In order to initiate a PCI Master read operation, the

FPGA application must supply the Master command,

Master read burst length, and PCI start address in the

specific order prescribed in Table 15 and Table 17, for

quad- and dual-port mode respectively. The bit defini-

tions of the Master command word are shown in

Table 10. This data is transferred via bus mwdata

(quad-port mode) or datafmfpga (dual-port mode), and

cannot be accepted by the Master FIFO interface

unless ma_fulln is inactive and m_ready is active. The

Master command word, Master read burst length, and

start address must be accompanied by assertion of the

enable maenn, with the command/address phase end-

ing with the assertion of mwlastcycn. After the com-

mand/address phase completes, ma_fulln goes active

indicating the Master will be begin negotiating for the

PCI bus.

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