OR3TP12 datasheet(17/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Parity

The PCI bus core implements all required and optional

features, including the following:

Master generates parity on all addresses placed on

the bus.

Sending agent generates parity on all data placed on

the bus.

Target calculates parity on all addresses received

from the bus.

Receiving agent calculates parity on all data

received from the bus.

The detected parity error bit in the status register is

set whenever an agent calculates corrupted parity.

The signal perrn is generated whenever an agent

calculates corrupted data parity and the parity error

response bit is set in the PCI command register.

The signal serrn is generated whenever an agent

calculates a corrupt address parity.

66 MHz Operation

The PCI bus core is fully compliant to PCI Specification

requirements at all clock rates up to 66 MHz. All

33 MHz requirements are also met.

Timing Budget

The PCI bus core’s timing budget is summarized in

Table 4. Note that the 66 MHz timing requirements only

allow 5 ns for signal proagation (TPROP), as compared

to 10 ns at 33 MHz. The effect of the reduction is to

reduce also the number of agents that the bus can sup-

port, although the actual number is not specified in the

PCI Specification and is dependent on the design of

the hardware components. The four components of the

timing budget are TVAL (valid output delay), TPROP

(propagation time), TSU (input setup time), and TSKEW

(clock skew); of these, only TVAL and TSU are controlled

by the PCI component, and TPROP and TSKEW are sys-

tem parameters. Table 4 includes a third column (also

shown in the PCI Specification); this column indicates

the performance attainable if all 66 MHz requirements

are met except TPROP = 10 ns, which is the 33 MHz

value. In this case, the total budget increases from

15 ns (66 MHz) to 20 ns (50 MHz).

Table 4. Timing Budgets

64-Bit Addressing

The PCI bus core fully supports 64-bit addressing,

whether or not the PCI bus core is configured to utilize

the 64-bit data extension. When the PCI bus core is a

64-bit Target being addressed by 64-bit Master, the PCI

bus core will decode the address one cycle faster so

that dual-address operation will have no performance

impact; see PCI Specification 2.1, Section 3.10.1 for

details.

Section 3.10.1 of the PCI Specification 2.1 also states

that a Master that supports 64-bit addressing must

nevertheless generate requests utilizing a single

address instead of a dual-address when the upper

32 bits are all zeros. This shortens the request time by

one cycle when communicating with 32-bit Targets.

FIFO Memories and Control

The OR3TP12 embedded core contains four FIFO

memories and supporting control logic. Two FIFOs are

for the Master FIFO interface data and two for the Tar-

get FIFO interface data. These FIFOs are configured to

operate in 64-bit mode and can also carry byte enable

bits on a per-byte basis (e.g., a 64-bit FIFO actually

carries 64 bits of data and eight byte enable bits for a

total of 72 bits). All FIFOs have two relevant flags which

extend into the FPGA logic for user application (e.g., a

Target read FIFO on the FPGA side has Full and Full-4

flags extending into the FPGA logic). Clocking for the

FPGA port of all FIFOs is flexible, with options for dif-

ferent clocks for the Master and Target FIFOs, all

sourced by the FPGA logic.

Timing Element 33 MHz 50 MHz 66 MHz

Unit

Cycle Time

30.0

20.0

15.0

Valid Output

Delay

11.0

7.5

6.0

Propagation

Time

10.0

6.5

5.0

Input Setup Time

7.0

4.5

3.0

Clock Skew

2.0

1.5

1.0

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