OR3TP12 datasheet(79/128 Pages) AGERE

79 / 128 page

Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed Description (continued)

Table 22. Dual-Port Target Read

1. When treqn is deasserted high, the Target interface is idle.

2. When taenn is asserted low, a command/address phase is in progress.

3. taenn must be asserted low for command/address data to transfer and state to change.

4. taenn must be deasserted high and trdataenn must be asserted low to execute the data phase.

5. Next state = 0 if trlastcycn is asserted low (end of Target read data).

6. Next state = 0 if twlastcycn is asserted low (end of Target command/address phase).

Table 23. Quad-Port Target Read

1. When treqn is deasserted high, the Target interface is idle.

2. When treqn is asserted low, a command/address phase is in progress.

3. taenn must be asserted low for command/address data to transfer and state to change.

4. taenn must be deasserted high and trdataenn must be asserted low to execute the data phase.

5. Next state = 0 if trlastcycn is asserted low (end of Target read data).

6. Next state = 0 if twlastcycn is asserted low (end of Target command/address phase).

tstatecntr

Next State of

tstatecntr

Description

Data on Bus

datatofpgax[3:0]

datatofpga[31:0]

Data on Bus

datafmfpga[31:0]

Notes

Idle

XXXXXXXX16

—1

1 or 0

Address[31:0]

X2, Burst, Dual-Address,

PCIAddress[31:0]

PCIData[31:0]

2, 3, 4, 5,

Address[63:32]

X2, Burst, Dual-Address,

PCIAddress[63:32]

PCIData[63:32]

2, 3, 4, 5,

tstatecntr

Next State of

tstatecntr

Description

Data on Bus

twdata[17:0]

Data on Bus

trdata[15:0]

Notes

Idle

XX2, XXXX16

—1

1 or 0

Address[15:0]

Burst, Dual-Address,

PCIAddress[15:0]

PCIData[15:0]

2, 3, 4, 6

2 or 0

Address[31:16]

Burst, Dual-Address,

PCIAddress[31:16]

PCIData[31:16]

2, 3, 4, 5,

3 or 0

Address[47:32]

Burst, Dual-Address,

PCIAddress[47:32]

PCIData[47:32]

2, 3, 4, 6

Address[63:48]

Burst, Dual-Address,

PCIAddress[63:48]

PCIData[63:48]

2, 3, 4, 5,

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