OR3TP12 datasheet(69/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed Description (continued)

Example: Target Single Read I/O, Delayed Transaction

Figure 24 shows the timing on the PCI for a Target I/O read that is handled as a delayed transaction (deltrn = 0).

Three transactions are shown. The first is the initial read in which the Target latches the command, address, and

byte enables. The Target then issues a retry, obligating the remote Master to continue to issue that identical request

until data is transferred. Meanwhile, the latched information will be transferred to the FPGA application via the Tar-

get FIFO interface. In the second transaction, as shown in Figure 24, all subsequent read or write requests to

memory or I/O space will result in retries, until the read data FIFO becomes nonempty. The third transaction is the

final transaction that completes the transfer of read data. The timing on this third transaction is identical to the tim-

ing of the first except that trdyn accompanies stopn to indicate the disconnect with data.

The FPGA interface timing is shown in Figure 27 and Figure 28 for dual- and quad-port respectively. The FPGA

interface timing is similar for all Target reads and is described below in the Single Target Read FIFO Interface sec-

tion.

5-7547(F)

Figure 24. Target I/O Read, Delayed (PCI Bus, 32-Bit)

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Tb0

Tb1

Tb2

Tb3

Tb4

Tb5

Tb6

Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

ADRS

DATA

CMD

BEs

CMD BYTE ENABLES

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

TRANSACTION #1: ADDRESS, BYTE ENABLES,

AND COMMAND LATCHED AS A

DELAYED READ REQUEST.

TRANSACTION #2: DISCONNECTED WITHOUT DATA

BECAUSE READ OPERATION NOT COMPLETED.

TRANSACTION #3: DISCONNECTED WITH DATA

BECAUSE READ OPERATION COMPLETED.

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