OR3TP12 datasheet(75/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed Description (continued)

For quad-port mode (Figure 28), the address is transferred on the bus twdata in 16-bit segments. If necessary, the

address will be split into two 16-bits components with the LSB being transferred first. A burst operation and dual-

address indication accompanies the address on twdata[17] and twdata[16] respectively. Assuming a BAR size

greater than 16 bits, the address phase will require two clock cycles, and twlastcycn will be asserted on the final or

MSB component of the address. The data phase will also require two clock cycles to transfer every 32-bit read data

word across the 16-bit bus from the FPGA application. trlastcycn will be deasserted for all 16-bit components of

the write data phase, except for the final 16-bit component where it is asserted. trlastcycn can only be asserted

when trdataenn is asserted. See Read Data Transfer section for details on trlastcycn.

Example: Target Read Memory Burst, Delayed Transaction

Figure 30 shows the timing on the PCI bus for a Target memory burst read of four 32-bit words handled as a

delayed transaction (deltrn = 0). On the PCI interface (Figure 30), three transactions are shown. In the first, the

Target responds to the request after determining that the address matches one of its BARs by asserting devseln.

However, since delayed transaction has been specified by the FPGA application (deltrn = 0), the Target issues a

retry since the Target read FIFO is empty. The Target waits for the FPGA application to load the Target read FIFO.

Until this occurs, all memory and I/O accesses result in retries as shown by the second transaction in Figure 30.

After the required read data is loaded, the actual data transfer will occur as shown in the third transaction in

Figure 30.

The FPGA interface timing is as shown in Figure 31 and Figure 32 for dual- and quad-port respectively. The Target

FIFO interface timing to the FPGA application is similar for all Target burst reads and is described below for the Tar-

get Read Burst FIFO interface.

5-7551(F)

Figure 30. Target Burst Memory Read, Delayed (PCI Bus, 32-Bit)

TRANSACTION #1: ADDRESS, BYTE ENABLES,

AND COMMAND LATCHED AS A

DELAYED READ REQUEST.

TRANSACTION #2: DISCONNECTED WITHOUT

DATA BECAUSE READ OPERATION

TRANSACTION #3: DISCONNECTED WITH DATA

BECAUSE READ OPERATION COMPLETED.

Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9

ADRS

CMD

BEs

CMD

BYTE ENABLES

CMD

BYTE ENABLES

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

ad_del

NOT COMPLETED.

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