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OR3TP12 Datasheet(PDF) 97 Page - Agere Systems |
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OR3TP12 Datasheet(HTML) 97 Page - Agere Systems |
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97 / 128 page  Lucent Technologies Inc. 97 Data Sheet ORCA OR3TP12 FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. Timing Characteristics (continued) Table 37. OR3TP12 FPGA Side Interface Clock to Output Delays, pciclk Synchronous Signals OR3TP12 Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C. Note: The clock to out parameters are measured from the pciclk clock output pin on the FPGA side, excluding the interbufs, which traverse the ASIC/FPGA boundary. The ORCA Foundry static analysis tool, trace, accounts for clock skew and interbuf delays on the clock and data paths. Table 38. OR3TP12 FPGA Side Interface Clock to Output Delays, fclk Synchronous Signals OR3TP12 Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C. Note: The clock to out parameters are measured from the fclk1 and fclk2 clock input pins on the FPGA side, excluding the interbufs, which traverse the ASIC/FPGA boundary. The ORCA Foundry static analysis tool, trace, accounts for clock skew and interbuf delays on the clock and data paths. Description (TI = 85 °C, VDD = min, VDD2 = min) Min Max Unit tcmd[3:0] — 5.124 ns bar[2:0] — 4.586 ns pci_cfg_stat — 11.383 ns Description (TI = 85 °C, VDD = min, VDD2 = min) Min Max Unit fpga_msyserror — 3.468 ns ma_fulln — 4.230 ns mstatecntr[3:0] — 5.049 ns m_ready — 4.996 ns mw_fulln — 4.918 ns mw_afulln — 4.056 ns datatofpga[31:0] (dual-port mode) — 12.514 ns datatofpgax[3:0] (dual-port mode) — 11.347 ns mrdata[17:0] (quad-port mode) — 12.514 ns twdata[17:0] (quad-port mode) — 11.229 ns mr_emptyn — 4.302 ns mr_aemptyn — 4.169 ns mrlastcycn — 8.835 ns disctimerexpn — 3.673 ns treqn — 5.643 ns t_ready — 4.779 ns tstatecntr[3:0] — 5.716 ns tw_emptyn — 4.741 ns tw_aemptyn — 4.360 ns twlastcycn — 10.212 ns tr_fulln — 4.554 ns tr_afulln — 4.216 ns trlastcycn — 6.154 ns |
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