OR3TP12 datasheet(74/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed Description (continued)

Example: Target Read Memory, Single-Word, Nondelayed Transaction

Figure 29 shows the timing on the PCI bus for a Target single memory read that is handled as nondelayed

(deltrn = 1, trburstpendn = 0); that is, the operation waits on the PCI bus while the FPGA application is notified via

the Target FIFO Interface. The Target accepts the transaction without issuing an immediate retry, but inserts wait-

states (up to 16 or 32) until data is in placed in the Target read FIFO. If the FPGA application cannot provide data

within the initial latency time, the Target issues a retry. The Target terminates the single read request normally with

data on the first word transformed.

5-7548(F).

Figure 29. Target Memory Read Single, Nondelayed Transaction (PCI Bus, 32-Bit)

Single Target Read FIFO Interface

The FIFO interface timing is as shown in Figure 27 and Figure 28 for dual- and quad-port respectively. The Target

FIFO interface timing to the FPGA application is similar for all Target reads: delayed Target I/O read, nondelayed

Target I/O read, delayed Target memory read, and nondelayed Target memory read. The timing on the FIFO inter-

face (Figure 27 for dual-port) shows the first indication to the FPGA application that a new operation has begun by

the assertion of Target request (treqn). The FPGA application begins the command/address phase by asserting

Target address enable (taenn) and accepting the command from the tcmd bus and address from bus datatofpga

(with fifo_sel = 1). A burst operation and dual-address indication accompanies the address on datatofpgax[1] and

datatofpgax[0] respectively. The FPGA application continues to receive address data until twlastcycn is asserted

indicating the end of the command/address phase. See command/address section for notes regarding address

transfer and alignment.

The read data phase will follow, by deassertion of taenn, and assertion of Target read data enable (trdataenn).

trdataenn can only be asserted while tr_fulln is deasserted, indicating that space is available in the read data

FIFOs. While trdataenn is asserted, the FPGA application will transfer Target read data on bus datafmfpga to the

read data FIFOs. The FPGA application is informed when the last component of the data phase was received when

trlastcycn is asserted. In a single access on a 32-bit PCI bus (pci_64bit = 0), this is on the first data phase.

Assuming this is a single access, (datatofpgax[1] = 0 during command/address phase), the first and only data

phase is the last data of the read data phase. After receiving trlastcycn at the end of the data phase, trdataenn

must be deasserted by the FPGA application. trlastcycn can only be asserted when trdataenn is asserted. See

Read Data Transfer section for details on trlastcycn.

Tn0

Tn1

Tn2

Tn3

ADDRESS

DATA

MEM RD

BYTE ENABLES

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

devseln

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