OR3TP12 datasheet(95/128 Pages) AGERE

95 / 128 page

Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 33. OR3TP12 PCI and FPGA Interface Clock Operation Frequencies

OR3TP12 Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C.

* The PCI clock frequency is based on the internal register to register frequency and the 66 MHz PCI I/O specifications.

† The Maximum User Interface Clock frequencies are values based on registering all signals at the FPGA/ASIC boundary. This number

will be lower depending on the design implementation and number of FPGA logic levels into and out of the ASIC.

‡ This is the typical operating frequency for a real design that does not register signals at the FPGA/ASIC boundary.

Table 34. OR3TP12 FPGA to PCI, and PCI to FPGA, Combinatorial Path Delays

OR3TP12 Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C.

Notes:

On the FPGA to PCI combinatorial path delays, they include the ASIC path delay and the output buffer delay under a

10pf load. They do not include the interbuf delay on the FPGA side.

On the PCI to FPGA combinatorial path delays, they include the ASIC input buffer delay, and ASIC path delay entering the

FPGA. They do not include the interbuf delay on the FPGA side.

Description

(TI = 85 °C, VDD = min, VDD2 = min)

Speed

–7

Unit

Signal

Min

Typ

Max

Clk (PCI clock)

—*

66*MHz

fclk1 (user interface clock)

—

†

‡

MHz

fclk2 (user interface clock)

—

†

‡

MHz

Description

(TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

Source

Destination

pci_intan (FPGA Side)

intan (PCI Side)

—

4.601

clk (PCI Side)

pciclk (FPGA Side)

—

4.544

rstn (PCI Side)

pci_rstn (FPGA Side)

—

2.442

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