OR3TP12 datasheet(25/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Target FIFO Address and Command Register Control Signals

treqn

Target Request from PCI. The Target asserts treqn as an indication to the

FPGA application that a PCI Target operation has been decoded and is pend-

ing. treqn signal will continue to be active until all data has been transferred

between the FPGA application and the Target FIFO interface. The FPGA appli-

cation should use treqn to qualify valid data on following buses: tcmd, bar,

twdata (quad-port mode), and datatofpga/datatofpgax (dual-port mode)

fclk*

taenn

Target Address Output Enable. This active-low signal enables the PCI start

address to be transferred from the Target address FIFO to the FPGA applica-

tion, on either bus twdata (quad-port mode) or datatofpga (dual-port mode,

fifo_sel = 1). treqn will be asserted to indicate a valid PCI Target address

exists.

fclk*

tcmd[3:0]

Target Command Code. This bus provides the PCI command code for a

pending Target operation, and is valid when treqn is asserted active-low.

—

bar[2:0]

Base Address Register Number. This bus indicates which of the six BARs

decoded the PCI address for the current Target operation, and is valid when

treqn is active-low. For 64-bit addresses, the BARs pairs will be indicated by

numbers 0, 2, and 4.

—

Target Write Data FIFO Signals

twdataenn

Target Write FIFO Data Enable. This active-low signal enables data from the

Target write data FIFO onto bus twdata (quad-port mode) or datatofpga (dual-

port mode, fifo_sel = 1). twdataenn should not be asserted whenever the Tar-

get write data FIFO is empty (tw_emptyn = 0).

fclk*

twdata[17:0]

(quad-port mode)

datatofpgax[3:0],

datatofpga[31:0]

(dual-port mode)

Depending on the OR3TP12 configuration, only one of these buses will be

available to the FPGA application. For Target operations, these buses will carry

the same information, but in different sizes and bit lanes as summarized below:

Quad-Port Mode

Dual-Port Mode (fifo_sel = 1)

a. Target Start Address: 32- or 64-bit PCI start address.

Address:

twdata[15:0]

datatofpga[31:0]

Dual-Address Indication:

twdata[16]

datatofpgax[0]

Burst Indication:

twdata[17]

datatofpgax[1]

Unused:

datatofpgax[3:2]

b. Target Write Data: Write data from PCI bus.

Data:

twdata[15:0]

datatofpga[31:0]

Write Enables:

twdata[17:16]

datatofpgax[3:0]

fclk*

tw_aemptyn

Target Write FIFO Almost Empty. This active-low signal indicates that only

four more 64-bit data locations are available to be read from the Target write

data FIFO.

fclk*

tw_emptyn

Target Write FIFO Empty. This active-low signal indicates that the Target write

FIFO is empty. twdataenn should never be asserted if tw_emptyn is asserted.

fclk*

* The source of the clock (fclk1 or fclk2) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.

PCI Bus Core Detailed Description (continued)

Table 6. Embedded Core/FPGA Interface Signals (continued)

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