OR3TP12 datasheet(33/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description (continued)

Embedded Core/FPGA FIFO Interface Operation Summary

The following sections describe the Master and Target FIFO interface operation between the PCI bus core and the

FPGA application. Table 9 is an index to the state tables and timing figures provided for each of the operational

modes (dual-port, quad-port) of the FIFO interface.

Table 9. Index to State Sequence Tables

* The FPGA interface does not participate in Target configuration operations.

Dual-Port Mode

Quad-Port Mode

Master/

Target

PCI

Access

Type

Address

Type

Single/Burst and

Delayed/

Nondelayed

PCI

Bus

Timing

Figure

State

Table

FPGA

Bus

Timing

Figure

State

Table

FPGA

Bus

Timing

Figure

Master

Write

Config,

Memory, I/O

Single

Burst

Read

Config,

Memory, I/O

Single

Burst

Target

Write

Config

Single

I/O

Single, Delayed

—

Single,

Nondelayed

Memory

Single

Burst

Read

Config

Single

I/O

Delayed

Nondelayed

Memory

Single

Single, Delayed

Burst

Burst, Delayed

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