OR3TP12 datasheet(22/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

Symbol

I/O

Description

Clock

Domain

Master Write Data FIFO Signals

mwlastcycn

Master Write Last Data Cycle. This active-low signal has two functions:

a. It is asserted low to indicate that the current Master start address word is the

final portion being sent. It can be asserted prior to any address portion being

transferred, indicating to use the previous stored address in the selected

Master holding register. maenn must be asserted with mwlastcycn during

the final address word.

b. It is asserted low to indicate that the accompanying Master write data is the

final data for this operation. mwdataenn must be asserted with mwlastcycn

during the final data word.

fclk*

mwdataenn

Master Write FIFO Data Enable. This active-low signal enables the registering

of data bus mwdata (quad-port mode) or datafmfpga (dual-port mode) during

Master write operations into the Master write data FIFOs. mwdataenn should

not be asserted when the Master write data FIFOs are full, or data may be lost.

fclk*

mwpcihold

Master Write PCI Bus Hold. For Master write transfers on the PCI bus, this

signal delays the start of the transfer (i.e., reqn asserted) on the PCI bus,

allowing the FPGA application to fill the Master write data FIFO. The transac-

tion will begin when mwpcihold is deasserted or the Master write data FIFO

becomes full. mwpcihold should be deasserted before mwlastcycn is

asserted, and needs to remain asserted for a minimum of two pciclk cycles.

pciclk

mw_afulln

Master Write Data FIFO Almost Full Flag. This active-low signal indicates

that only four more empty 64-bit locations remain in the Master write data

FIFO.

fclk*

mw_fulln

Master Write Data FIFO Full Flag. This active-low signal indicates that the

Master write data FIFO is full. mwdataenn should never be asserted when

mw_fulln is active.

fclk*

* The source of the clock (fclk1 or fclk2) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.

PCI Bus Core Detailed Description (continued)

Table 6. Embedded Core/FPGA Interface Signals (continued)

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