OR3TP12 datasheet(13/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description

The following sections describe the operation of the embedded PCI bus core interface.

PCI Bus Commands

The PCI bus core supports all commands required by the PCI Specification. The following table describes each

command. Subsequent sections will describe the protocols in which the commands are used.

Table 3. PCI Bus Command Descriptions

Command

Code

(Binary)

Command

OR3TP12

Master

Generates

OR3TP12

Target

Accepts

Description

0000

Interrupt

Acknowledge

—

Only implemented by Master agents that interface to the

system CPU and as Target by agents that incorporate the

system interrupt controller.

0001

Special Cycle

—

Target ignores, per PCI Specification Section 3.7.2.

0010

I/O Read

√√

Target: Single accesses only, with bursts disconnected

after first data phase.

Delayed Mode (deltrn = 0): Terminates the initial access

with a retry, recording internally the PCI address and byte

enables for processing by the FPGA application. Subse-

quent PCI accesses occurring before the FPGA application

loads the Target read FIFO continues to result in retries.

After the Target read FIFO is loaded by the FPGA applica-

tion, the next read access that matches the stored parame-

ters disconnects with the FPGA supplied data and the

Target read logic is cleared.

Nondelayed Mode (deltrn = 1, trburstpendn = 0):

Accepted access inserts wait-states up to the initial latency

count (16 or 32 clocks depending on the option selected in

the FPSC configuration manager). During the wait-states,

the FPGA application processes the read request and

transfers data into the Target read FIFOs. If read data is

transferred into the Target read FIFOs before the latency

count expires, this read data is transferred to the PCI bus

during initial request. If not, the PCI address, byte enables,

and Target read data remain stored in the Target controller.

The next access that matches the stored address and byte

enables disconnects with the FPGA supplied data, and the

Target read logic is cleared.

Master: Single and burst operations are allowed.

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