OR3TP12 datasheet(61/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed Description (continued)

5-7362(F)

Figure 19. Target Write Single (FIFO Interface, Quad-Port)

Example: Target Write Memory Burst Transaction

Figure 20 shows the timing on the PCI bus for a Target memory write burst of four 32-bit words. The timing on the

PCI interface is typical for a medium-speed decode Target. Note that trdyn is asserted at the earliest possible time,

which is concurrent with assertion of devseln. In the example of a 4-word burst, the Target write FIFO is not filled,

so execution continues to completion. This would also be the case for a burst of any length when the FPGA appli-

cation is capable of unloading the FIFO as fast as the PCI interface is loading it. If the Target write FIFO becomes

full, the Target can disconnect without data on the first data word it cannot accept (twburstpendn = 1), or insert up

to eight wait-states (twburstpendn = 0).

The timing on the dual-port FIFO interface (Figure 21) shows the first indication to the FPGA application that a new

operation has begun by the assertion of Target request (treqn). When treqn is valid, the FPGA application begins

the command/address phase by asserting Target address enable (taenn) and accepting the command from bus

tcmd and address from bus datatofpga(x) (with fifo_sel = 1). A burst operation and dual-address indication

accompanies the address on datatofpgax[1] and datatofpgax[0] respectively. The FPGA application continues to

receives new address data (taenn asserted) on every clock until twlastcycn is asserted, indicating the end of the

command/address phase. See command/address section for notes regarding address transfer and alignment.

T2T3T4T5

CMD

ADRS0

ADRS1

fclk

tstatecntr

t_ready

treqn

tcmd

twdata

taenn

tw_emptyn

twdataenn

twlastcycn

OR3TP12 Datasheet(PDF) 61 Page - Agere Systems