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OR3TP12 Datasheet(PDF) 68 Page - Agere Systems |
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OR3TP12 Datasheet(HTML) 68 Page - Agere Systems |
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68 / 128 page  ORCA OR3TP12 FPSC Data Sheet Embedded Master/Target PCI Interface March 2000 68 Lucent Technologies Inc. Lucent Technologies Inc. PCI Bus Core Target Controller Detailed Description (continued) Example: Target Read from Configuration Space Figure 23 shows the timing on the PCI interface for a Target read from configuration space. Accesses of configura- tion space occurs without any involvement of the FPGA interface. All configuration space accesses are discon- nected with data on the first data word, and are thus restricted from bursting. Address decode speed is medium, and the PCI bus core signals that it is supplying the word of data by asserting trdyn one cycle after devseln is asserted. 5-7375(F) Figure 23. Target Configuration Read (PCI Bus, 32-Bit) T0 T1 T2 T3 T4 T5 T6 ADDRESS DATA CFG RD BYTE ENABLES clk framen ad c_ben idsel irdyn devseln trdyn stopn |
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