OR3TP12 datasheet(52/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Master Controller Detailed Description (continued)

Table 16. Quad-Port Master Read, Duplicate Burst Length

1. When maenn, mrdataenn, and ma_fulln are deasserted high, the Master interface is idle.

2. When maenn is asserted low, a command/address phase is in progress.

3. maenn must be asserted low for command/address data to transfer and state to change.

4. maenn must be deasserted high and mrdataenn must be asserted low to execute the read data phase.

5. Next state = 0 if mrlastcycn is asserted low (end of Master read data phase).

6. Next state = 0 if mwlastcycn is asserted low (end of Master command/address phase).

Table 17. Quad-Port Master Read, Specified Burst Length

1. When maenn, mrdataenn, and ma_fulln are deasserted high, the Master interface is idle.

2. When maenn is asserted low, a command/address phase is in progress.

3. maenn must be asserted low for command/address data to transfer and state to change.

4. maenn must be deasserted high and mrdataenn must be asserted low to execute the read data phase.

5. Next state = 0 if mrlastcycn is asserted low (end of Master read data phase).

6. Next state = 0 if mwlastcycn is asserted low (end of Master command/address phase).

MStateCntr

Next State of

MStateCntr

Description

Data on Bus

mwdata[17:0]

Data on Bus

mrdata[15:0]

Notes

Idle

XX2 XXXX16

—1

1 or 0

Command Word

or Data[15:0]

Command Word

PCIData[15:0]

2, 3, 4, 5, 6

2 or 0

Address[15:0] or

Data[31:16]

XX2, PCIAddress[15:0]

PCIData[15:0]

2, 3, 4, 5, 6

3 or 0

Address[31:16] or

Data[47:32]

XX2, PCIAddress[15:0]

PCIData[47:32]

2, 3, 4, 5, 6

4 or 0

Address[47:32] or

Data[63:48]

XX2, PCIAddress[47:32]

PCIData[63:48]

2, 3, 4, 5, 6

Address[63:48]

XX2, PCIAddress[63:48]

—

2, 3, 6

MStateCntr

Next State of

MStateCntr

Description

Data on Bus

mwdata[17:0]

Data on Bus

mrdata[15:0]

Notes

Idle

XX2 XXXX16

—1

Command Word

or Data[15:0]

Command Word

PCIData[15:0]

2, 3, 4, 5, 6

2 or 0

Burst Length or

Data[31:16]

Burst Length

PCIData[31:16]

2, 3, 4, 5, 6

3 or 0

Address[15:0] or

Data[47:32]

XX2, PCIAddress[15:0]

PCIData[47:32]

2, 3, 4, 5, 6

4 or 0

Address[31:16] or

Data[63:48]

XX2, PCIAddress[15:0]

PCIData[63:48]

2, 3, 4, 5, 6

5 or 0

Address[47:32] or

Data[63:48]

XX2, PCIAd-

dress[47:32]

—

2, 3, 6

Address[63:48]

XX2, PCIAd-

dress[63:48]

—

2, 3, 6

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