OR3TP12 datasheet(56/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed

Description (continued)

Write Data Transfer

The FPGA application enters the write data phase by

deasserting taenn and asserting twdataenn. On every

cycle that twdataenn is asserted, the FPGA applica-

tion receives write data and its associated byte enables

from the Target write data FIFO (64 32-bit words; 32

64-bit words) via bus twdata (quad-port mode) or

datatofpga (dual-port mode with fifo_sel = 1), provid-

ing the write data FIFOs are not empty (tw_emptyn =

1). twdataenn must not be asserted when the write

data FIFOs are empty (tw_emptyn is asserted). Note

that tw_emptyn can be updated on the same clock

edge as twdataenn is sampled.

The distinction between a burst write and a single

access is provided by the burst indication bit

(twdata[17] (quad-port); datatofpgax[1] (dual-port

with fifo_sel = 1), or behavior of the twlastcycn signal

during the data phase. When twlastcycn is asserted,

this signal informs the FPGA application of the end of

the write data phase. twlastcycn will remain deas-

serted with every write data element except the last

element on bus twdata (quad-port mode) or datatof-

pga (dual-port mode with fifo_sel = 1). For example,

on a single 32-bit word transfer in dual-port mode,

twlastcycn would be asserted during the entire write

data phase, since the last data phase is the only data

phase of this transfer.

When executing on a 64-bit PCI bus (pci_64bit = 1) or

a burst Target write, the write data transferred from the

FPGA application is aligned on 64-bit address bound-

aries. This alignment may transfer extra padding data

from the FIFOs for activity during 32-bit PCI transfers.

For transfers starting at an odd 32-bit PCI address

(ad2 = 1), the FPGA application will receive a 32-bit

padding data word at the beginning of the write data

phase. For burst transfers starting at an even PCI

address (ad2 = 0) with an odd number of 32-bit data

words, a 32-bit padding data word will be received at

the end of the data phase. Padding data words are indi-

cated by data words with all of its byte enables deas-

serted.

For single 32-bit transactions (Burst indication bit deas-

serted) on 32-bit PCI buses (pci_64bit = 0), the Target

FIFO interface will perform proper data alignment. Dur-

ing the data phase, the FPGA application will only

receive the 32-bit data word, and no padding words are

present.

Target Write Data FIFO Empty/Almost Empty

When the Target write FIFO contains four or fewer

64-bit data elements, the Target FIFO interface asserts

tw_aemptyn the FIFO almost empty indicator. This

allows some latency to exist in the FPGA’s response

without risking overreading the FIFO. When the FPGA

application has read all data out of the Target write

FIFO, the Target FIFO interface asserts tw_emptyn,

the FIFO empty indicator. Since data can be simulta-

neously written to, and read from, the Target write

FIFO, both tw_aemptyn and tw_emptyn can change

states in either direction multiple times in the course of

a burst data transfer.

Target Write Termination

Target write termination will be by normal Master termi-

nation, disconnect associated with a full Target write

data FIFO, retry associated with a pending Target

transaction, or a reset by rstn.

On the Target FIFO interface, twlastcycn signals when

the last item remaining in the Target write FIFO has

been received by the FPGA application (although the

actual PCI bus transaction may have completed much

earlier). The Target FIFO interface then signals end of

transaction to the FPGA application by deasserting

treqn for at least one clock. If treqn subsequently reas-

serts, this indicates a new, unrelated transaction.

Reset

The FPGA application can apply a reset signal to place

the Target FIFO interface logic in a known state, clear-

ing the Target FIFOs and resetting tstatecntr. The

reset signal, tfifoclrn, is asynchronous and therefore

should be asserted for a minimum of one clock cycle

and deasserted for a minimum of one clock cycle

before continuing.

It is not recommended to assert tfifoclrn while a cur-

rent PCI transaction is in progress (treqn is asserted),

since proper PCI bus termination is not guaranteed.

Only rstn will reset the internal Target PCI state

machines, while a PCI transaction is in progress.

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