OR3TP12 datasheet(98/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 39. OR3TP12 FPGA Side Interface Input Setup Delays, pciclk Synchronous Signals

OR3TP12 Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C.

Note: The input setup parameters are measured from the pciclk clock output pin on the FPGA side, excluding the interbufs, which traverse the

ASIC/FPGA boundary. The

ORCA Foundry static analysis tool, trace, accounts for clock skew and interbuf delays on the clock and data

paths.

Table 40. OR3TP12 FPGA Side Interface Input Setup Delays, fclk Synchronous Signals

OR3TP12 Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C.

Note: The input setup parameters are measured from the fclk1 and fclk2 clock input pins on the FPGA side, excluding the interbufs, which

traverse the ASIC/FPGA boundary. The

ORCA Foundry static analysis tool, trace, accounts for clock skew and interbuf delays on the

clock and data paths.

Description

(TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

fpga_mbusyn

0—

deltrn

0—

mwpcihold

3.943

—

mr_mstopburstn

0—

t_abort

1.197

—

t_retryn

0.795

—

twburstpendn

0—

trpcihold

0.693

—

trburstpendn

0—

fpga_syserror

0—

cfgshiftenn

0—

Description

(TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

maenn

6.426

—

mwdataenn

6.452

—

datafmfpga[31:0] (dual-port mode)

7.344

—

datafmfpgax[3:0] (dual-port mode)

5.226

—

mwdata[17:0] (quad-port mode)

7.205

—

trdata[17:0] (quad-port mode)

7.344

—

mwlastcycn

6.680

—

mrdataenn

5.371

—

taenn

5.048

—

twdataenn

5.099

—

trdataenn

5.919

—

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