OR3TP12 datasheet(38/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Master Controller

Detailed Description (continued)

Termination

Once initiated, Master write operations will continue on

the PCI bus until either all write data is sent, an abort

occurs (either Master or Target), or the PCI bus’ reset

signal (rstn) is asserted. During aborts, the Master

address and write data FIFOs will be cleared, and the

FPGA application will be notified by the assertion of

fpga_msyserror.

If the Master write transaction is terminated with a retry

or disconnected by the external Target before all data

has been transferred, the Master will initiate another

Master write operation, continuing from that point using

a stored address pointer.

On the Master FIFO interface, the FPGA application

identifies the last data word by asserting mwlastcycn.

When this data word is transferred to the PCI bus, the

Master will terminate the PCI transaction normally. The

Master will inform the FPGA application of completion

by deasserting ma_fulln.

Reset

The FPGA application can apply a reset signal to place

the Master FIFO interface logic in a known state, which

clears all FIFOs and mstatecntr. The reset signal,

mfifoclrn, is asynchronous and therefore should be

asserted for a minimum of one clock cycle and deas-

serted for a minimum of one clock cycle before continu-

ing. This is not recommended to assert mfifoclrn while

a current PCI transaction is in progress (ma_fulln

asserted), since proper PCI bus termination is not

guaranteed. Only PCI rstn will reset the internal Master

PCI state machines, while a PCI transaction is in

progress.

OR3TP12 Datasheet(PDF) 38 Page - Agere Systems