OR3TP12 datasheet(4/128 Pages) AGERE

4 / 128 page

Tables

Page

Tables

Page

ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

List of Tables

Table 1. PCI Local Bus Data Rates ...........................1

Table 2.

ORCA PCI FPSC Solutions—

Available FPGA Resources ..................................1

Table 3. PCI Bus Command Descriptions ...............13

Table 4. Timing Budgets ..........................................17

Table 5. PCI Bus Pin Descriptions ...........................18

Table 6. Embedded Core/FPGA

Interface Signals ................................................21

Table 7. OR3TP12 FPGA/PCI Core

Interface Signal Locations..................................29

Table 8. PCI Bus Core Options Settable

via FPGA Configuration RAM Bits ....................31

Table 9. Index to State Sequence Tables.................33

Table 10. Bit Definitions for Master

Command/Address Phase .................................35

Table 11. Holding Registers,

Examples of Typical Operation...........................36

Table 12. Master State Counter (MStateCntr)

Values and the Corresponding Bus Data ...........36

Table 13. Dual-Port Master Writes...........................43

Table 14. Quad-Port Master Writes .........................43

Table 15. Dual-Port Master Read,

Specified Burst Length .......................................51

Table 16. Quad-Port Master Read,

Duplicate Burst Length.......................................52

Table 17. Quad-Port Master Read,

Specified Burst Length .......................................52

Table 18. Bit Destinations for Target

Command/Address Phase .................................54

Table 19. Target State Counter (TStateCntr)

Values and the Corresponding Bus Data ...........55

Table 20. Dual-Port Target Write..............................64

Table 21. Quad-Port Target Write ............................65

Table 22. Dual-Port Target Read .............................79

Table 23. Quad-Port Target Read ............................79

Table 24. Configuration Space Layout .....................82

Table 25. Configuration Space Assignment.............83

Table 26. Configuration Frame

Format and Contents .........................................89

Table 27. Configuration Frame Size.........................90

Table 28. Configuration Modes ................................90

Table 29. Absolute Maximum Ratings .....................91

Table 30. Recommend Operating Conditions ..........91

Table 31. Electrical Characteristics..........................92

Table 32. Derating for Commercial Devices

(I/O Supply VDD) ................................................93

Table 33. OR3TP12 PCI and FPGA Interface

Clock Operation Frequencies .............................95

Table 34. OR3TP12 FPGA to PCI, and PCI to

FPGA, Combinatorial Path Delays .....................95

Table 35. OR3TP12 FPGA Side Interface

Combinatorial Path Delay Signals......................96

Table 36. OR3TP12 Interbuf Delays ........................96

Table 37. OR3TP12 FPGA Side Interface Clock to

Output Delays, pciclk Synchronous Signals.......97

Table 38. OR3TP12 FPGA Side Interface Clock to

Output Delays, fclk Synchronous Signals ..........97

Table 39. OR3TP12 FPGA Side Interface Input

Setup Delays, pciclk Synchronous Signals ........98

Table 40. OR3TP12 FPGA Side Interface Input

Setup Delays, fclk Synchronous Signals............98

Table 41. FPGA Common-Function

Pin Descriptions ...............................................102

Table 42. OR3TP12 240-Pin SQFP2 Pinout..........105

Table 43. OR3TP12 256-Pin PBGA Pinout............109

Table 44. OR3TP12 352-Pin PBGA Pinout............113

Table 45.

ORCA OR3TP12 Plastic Package

Thermal Guidelines..........................................120

Table 46.

ORCA OR3TP12 Package Parasitics.....121

Table 47. Voltage Options ......................................126

Table 48. Temperature Options..............................126

Table 49. Package Options ....................................126

Table 50.

ORCA Series 3+ Package Matrix ...........126

Table 51. Embedded Core Type.............................126

Table 52. FPSC Base Array ...................................126

OR3TP12 Datasheet(PDF) 4 Page - Agere Systems

OR3TP12 Datasheet(HTML) 4 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL