OR3TP12 datasheet(104/128 Pages) AGERE

104 / 128 page

ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

104

Lucent Technologies Inc.

Symbol

I/O

Description

Special-Purpose Pins (continued)

MPI_IRQ

I/O

MPI active-low interrupt request output.

If the MPI is not in use, this is a user-programmable I/O.

MPI_BI

I/O

PowerPC mode MPI burst inhibit output.

If the MPI is not in use, this is a user-programmable I/O.

MPI_ACK

OIn

PowerPC mode MPI operation, this is the active-high transfer acknowledge (TA) out-

put. For

i960 MPI operation, it is the active-low ready/record (RDYRCV) output.

If the MPI is not in use, this is a user-programmable I/O.

MPI_RW

I/O

PowerPC mode MPI operation, this is the active-low write/ active-high read control

signals. For

i960 operation, it is the active-high write/active-low read control signal.

If the MPI is not in use, this is a user-programmable I/O.

MPI_CLK

I/O

This is the clock used for the synchronous MPI interface. For

PowerPC, it is the CLK-

OUT signal. For

i960, it is the system clock that is chosen for the i960 external bus inter-

face.

If the MPI is not in use, this is a user-programmable I/O.

A[4:0]

I/O

For

PowerPC operation, these are the PowerPC address inputs. The address bit map-

ping (in

PowerPC/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/A[3], A[27]/

A[4]. Note that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in

i960 MPI mode.

If the MPI is not in use, this is a user-programmable I/O.

A[1:0]/MPI_BE[1:0]

For

i960 operation, MPI_BE[1:0] provide the i960 byte enable signals, be[1:0], that are

used as address bits A[1:0] in

i960 byte-wide operation.

D[7:0]

I/O

During Master parallel, peripheral, and slave parallel configuration modes, D[7:0]

receive configuration data, and each pin has a pull-up enabled. During serial configura-

tion modes, D0 is the DIN input. D[7:0] are also the data pins for

PowerPC microproces-

sor mode and the address/data pins for

i960 microprocessor mode.

After configuration, the pins are user-programmable I/O pins.*

DIN

I/O

During slave serial or Master serial configuration modes, DIN accepts serial configura-

tion data synchronous with CCLK. During parallel configuration modes, DIN is the D0

input. During configuration, a pull-up is enabled.

After configuration, this pin is a user-programmable I/O pin.*

DOUT

I/O

During configuration, DOUT is the serial data output that can drive the DIN of daisy-

chained slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.

After configuration, DOUT is a user-programmable I/O pin.*

* The

ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release

is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all

user I/Os) is controlled by a second set of options.

Pin Information (continued)

Table 41. FPGA Common-Function Pin Descriptions (continued)

OR3TP12 Datasheet(PDF) 104 Page - Agere Systems

OR3TP12 Datasheet(HTML) 104 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL