DM504 datasheet(180/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

1. Use lowest inductance footprint and trace connection scheme possible for given PCB technology and

layout area in order to minimize Dcap loop inductance to power pin as much as possible (see Figure 7-

9).

2. Place Dcaps on “same-side” as component within their power plane outline to minimize “decoupling

loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB

layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify

minimum inductance for top vs bottom-side placement.

3. Place Dcaps on “opposite-side” as component within their power plane outline if “same-side” is not

feasible or if distance to power pin is greater than ~500mils for top-side location. Use PI modeling CAD

tool to verify minimum inductance for top vs bottom-side placement.

4. Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component

power pins, etc.).

5. Place all voltage and gnd plane vias “as close as possible” to point of use (i.e. Dcap pads, component

power pins, etc.).

6. Use a “Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small

number of vias within restricted PCB areas (i.e. underneath BGA components).

Frequency analysis for the CORE power domain (vdd) has yielded the Dcap Loop Inductance and

Impedance vs Frequency responses shown in Section 7.3.7.2, vdd Example Analysis.

7.2.5

System ESD Generic Guidelines

7.2.5.1

System ESD Generic PCB Guideline

Protection devices must be placed close to the ESD source which means close to the connector. This

allows the device to subtract the energy associated with an ESD strike before it reaches the internal

circuitry of the application board.

To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero

turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the low-

resistive, low-inductive path from the signal to the ground is granted and not increasing the impedance

between signal and ground.

For ESD protection array being railed to a power supply when no decoupling capacitor is available in close

vicinity, consider using a decoupling capacitor (

≥ 0.1 µF) tight to the VCC pin of the ESD protection. A

positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse.

Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and

GND in Figure 7-10) from connector to external protection because the interconnect may see between 15-

A to 30-A current in a short period of time during the ESD event.

DM504 Datasheet(PDF) 180 Page - Texas Instruments

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