DM504 datasheet(182/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

Figure 7-11. Trace Examples

•

Always route signal traces and their associated ground returns as close to one another as possible to

minimize the loop area enclosed by current flow:

–

At high frequencies current follows the path of least inductance.

–

At low frequencies current flows through the path of least resistance.

7.2.5.3

ESD Protection System Design Consideration

ESD protection system design consideration is covered in of this document. The following are additional

considerations for ESD protection in a system.

•

Metallic shielding for both ESD and EMI

•

Chassis GND isolation from the board GND

•

Air gap designed on board to absorb ESD energy

•

Clamping diodes to absorb ESD energy

•

Capacitors to divert ESD energy

•

The use of external ESD components on the DP/DM lines may affect signal quality and are not

recommended.

7.2.6

EMI / EMC Issues Prevention

All high-speed digital integrated circuits can be sources of unwanted radiation, which can affect nearby

sensitive circuitry and cause the final product to have radiated emissions levels above the limits allowed

by the EMC regulations if some preventative steps are not taken.

Likewise, analog and digital circuits can be susceptible to interference from the outside world and picked

up by the circuitry interconnections.

To minimize the potential for EMI/EMC issues, the following guidelines are recommended to be followed.

7.2.6.1

Signal Bandwidth

To evaluate the frequency of a digital signal, an estimated rule of thumb is to consider its bandwidth fBW

with respect to its rise time, tR:

fBW ≈ 0.35 / tR

This frequency actually corresponds to the break point in the signal spectrum, where the harmonics start

to decay at 40 dB per decade instead of 20 dB per decade.

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