ELANSC520 datasheet(118/440 Pages) AMD

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General-Purpose Bus Controller Registers

10-2

Élan™SC520 Microcontroller Register Set Manual

GP Echo Mode (GPECHO)

Memory-Mapped

MMCR Offset C00h

This register is used to enable the GP bus echo mode.

Bit Definitions

Programming Notes

While echo mode is enabled, the access timing to internal peripherals is modified to adhere to the external timings

programmed by the user. This ensures that external peripherals connected to the GP bus still work as programmed

by the user. Thus it is possible that access to internal peripherals are slower in echo mode than in normal mode.

While echo mode is enabled, the system designer must ensure that the GP bus timing is not faster than that shown

in Table 10-2. The table shows the minimum GP bus timing register values allowed in echo mode. See the

corresponding register descriptions beginning on page 10-7.

Bit

Reserved

GP_ECHO_

ENB

Reset

00000000

R/W

RSV

R/W

Bit

Name

Function

–1

Reserved

This field should be written to 0 for normal system operation.

GP_ECHO_

ENB

GP Bus Echo Mode Enable

This bit is used to enable the echo mode of GP bus.

0 = Echo mode is disabled.

1 = Echo mode is enabled. Accesses to the microcontroller’s integrated peripherals are

echoed to the external GP bus

Table 10-2

GP Bus Echo Mode Minimum Timing

Signal Type

Offset

Notes:

1. The actual time value is the register value plus one. Times are in units of one internal (33-MHz) clock period.

Pulse Width Register

Value1

Recovery Time

GP Chip Select

GP Read

—

GP Write

—

GPALE

—

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