ELANSC520 datasheet(121/440 Pages) AMD

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General-Purpose Bus Controller Registers

Élan™SC520 Microcontroller Register Set Manual

10-5

GP Chip Select Qualification (GPCSQUAL)

Memory-Mapped

MMCR Offset C02h

This register is used to qualify the GP bus chip selects with GPIORD, GPIOWR, GPMEMRD or GPMEMWR. The

qualifiers that can be used depend on the TARGET bit field in the PARx register for the addressed region (see

page 2-6). If the TARGET bit field selects GP bus I/O, the GP bus chip selects can be qualified with GPIORD or

GPIOWR. If the TARGET bit field selects GP bus memory, the GP bus chip selects can be qualified with GPMEMRD

or GPMEMWR.

Bit Definitions

Bit

GPCS7_RW[1–0]

GPCS6_RW[1–0]

GPCS5_RW[1–0]

GPCS4_RW[1–0]

Reset

00000000

R/W

Bit

GPCS3_RW[1–0]

GPCS2_RW[1–0]

GPCS1_RW[1–0]

GPCS0_RW[1–0]

Reset

00000000

R/W

Bit

Name

Function

–14

GPCS7_RW

[1–0]

GPCS7 Qualifier Selection

This field is used to qualify the GP bus chip select 7 with GPIORD, GPIOWR, GPMEMRD or

GPMEMWR.

00 = No qualification.

01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR)

10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD)

11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and

GPMEMWR)

–12

GPCS6_RW

[1–0]

GPCS6 Qualifier Selection

This field is used to qualify the GP bus chip select 6 with GPIORD, GPIOWR, GPMEMRD or

GPMEMWR.

00 = No qualification.

01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR)

10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD)

11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and

GPMEMWR)

–10

GPCS5_RW

[1–0]

GPCS5 Qualifier Selection

This field is used to qualify the GP bus chip select 5 with GPIORD, GPIOWR, GPMEMRD or

GPMEMWR.

00 = No qualification.

01 = Qualify the chip select with write strobes (GPIOWR or GPMEMWR)

10 = Qualify the chip select with read strobes (GPIORD or GPMEMRD)

11 = Qualify the chip select with both strobes (GPIORD and GPIOWR, or GPMEMRD and

GPMEMWR)

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