ELANSC520 datasheet(180/440 Pages) AMD

180 / 440 page

GP DMA Controller Registers

11-48

Élan™SC520 Microcontroller Register Set Manual

Slave DMA Channel 3 Memory Address (GPDMA3MAR)

Direct-Mapped

I/O Address 0006h

This register contains bits 15–0 of the memory address for Channel 3 during DMA operation.

Bit Definitions

Programming Notes

To ensure that the lower byte of this register (GPDMA3MAR) is always accessed first, software should precede any

access to this register with a write to the SLDMACBP register (see page 11-57) to clear the slave DMA byte pointer.

The value in this register (GPDMA3MAR) is used with the values in the GPDMA3PG register (see page 11-64) and

the GPDMAEXTPG3 register (see page 11-13) to generate DMA address bits 27–0.

In enhanced mode, this channel can be programmed for 16-bit DMA transfers (see the descriptions for GPDMACTL

(GPDMA3MAR) holds address bits 16–1 and address bit 0 is always 0 (i.e., the 16-bit transfers are word-aligned).

Because of this, software must load this register with the desired memory address divided by 2 for 16-bit transfers.

Bit

DMA3MAR[15

–0]

Reset

xxxxxxxx

R/W

R/W!

Bit

Name

Function

7–0

DMA3MAR

[15–0]

Lower 16 Bits of DMA Channel 3 Memory Address

This 8-bit field is used in two successive I/O accesses to read or write the channel’s memory

address bits 15–0.

Bits 7–0 of the channel’s memory address can be read from or written to this bit field

immediately after a write to the SLDMACBP register (see page 11-57).

Bits 15–8 of the channel’s memory address can be read from or written to this bit field

immediately after memory address bits 7–0 are read from or written to this bit field.

ELANSC520 Datasheet(PDF) 180 Page - Advanced Micro Devices