ELANSC520 datasheet(183/440 Pages) AMD

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GP DMA Controller Registers

Élan™SC520 Microcontroller Register Set Manual

11-51

Slave DMA Channel 0–3 Control (SLDMACTL)

Direct-Mapped

I/O Address 0008h

This register provides the control function for Channels 0–3.

Bit Definitions

Bit

DAKSEN

DRQSEN

WRTSEL

PRITYPE

COMPTIM

DMA_DIS

Reserved

Reset

00000000

R/W

WWWWWW

RSV

Bit

Name

Function

DAKSEN

Internal dackx Sense

In a discrete DMA controller, this bit controls the polarity of all dackx outputs from the slave

DMA controller:

0 = Asserted Low

1 = Asserted High

System logic external to the DMA controller expects the DMA controller to drive active Low

dackx outputs. This bit must be written to 0 for proper system operation.

DRQSEN

Internal drqx Sense

In a discrete DMA controller, this bit controls the polarity of all drqx inputs to the slave DMA

controller:

0 = Asserted High

1 = Asserted Low

System logic external to the DMA controller expects the DMA controller to respond to active

High drqx inputs. This bit must be written to 0 for proper system operation.

WRTSEL

Write Selection Control

0 = Late write selection.

1 = Extended (early) write selection. Write command signals (GPIOWR and GPMEMWR) are

asserted one clock early.

Enabling this feature results in timing changes on the GP bus that can violate the ISA

specification. This bit has no effect when the COMPTIM bit is 1.

PRITYPE

Priority Type

0 = Fixed priority

1 = Rotating priority

COMPTIM

Compressed Timing

0 = Normal timing.

1 = Compressed timing. Read command signals (GPIORD and GPMEMRD) have a one clock

pulse width.

Enabling this feature results in timing changes on the GP bus that can violate the ISA

specification.

2DMA_DIS

Disable DMA Controller

0 = DMA requests are enabled.

1 = DMA requests are ignored but DMA registers are available to the CPU.

The DMA controller should be disabled prior to programming it in order to prevent unintended

transfers from occurring during the DMA controller programming operation. Care should also

be taken to ensure that the DMA controller is idle before disabling it. If the DMA controller is

performing a transfer when software disables it, abnormal system operation can occur.

ELANSC520 Datasheet(PDF) 183 Page - Advanced Micro Devices

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