ELANSC520 datasheet(187/440 Pages) AMD

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GP DMA Controller Registers

Élan™SC520 Microcontroller Register Set Manual

11-55

Slave DMA Channel 0–3 Mode (SLDMAMODE)

Direct-Mapped

I/O Address 000Bh

This register indicates the transfer mode for Channels 0–3.

Bit Definitions

Bit

TRNMOD[1–0]

ADDDEC

AINIT

OPSEL[1–0]

MODSEL[1–0]

Reset

xxxxxxxx

R/W

Bit

Name

Function

7–6

TRNMOD[1–0]

Transfer Mode

This bit field selects the transfer mode for the channel selected by the MODSEL bit field.

00 = Demand transfer mode

01 = Single transfer mode

10 = Block transfer mode

11 = Cascade mode. (Only Channel 4 should be programmed for cascade mode. All other

channels should be programmed for one of the other modes).

ADDDEC

Address Decrement

This bit field selects increment or decrement counting for the channel selected by the

MODSEL bit field.

0 = Increment the DMA memory address after each transfer.

1 = Decrement the DMA memory address after each transfer.

4AINIT

Automatic Initialization Control

This bit field enables automatic initialization for the channel selected by the MODSEL bit field.

0 = Automatic initialization is disabled.

1 = Automatic initialization is enabled.

Automatic initialization causes the channel’s base address and transfer count registers to be

restored to the values they contained prior to the DMA transfer when the transfer count ends.

The channel is then ready to perform another DMA transfer without processor intervention as

soon as the next DMA request is detected.

Automatic initialization must be disabled when buffer chaining mode is used; otherwise

unexpected results may occur.

3–2

OPSEL[1–0]

Operation Select

This bit field selects the DMA operation for the channel selected by the MODSEL bit field.

00 = Verify mode. The DMA controller acts normally except that no I/O or memory commands

are generated, and no data is transferred.

01 = Write transfer. Data is transferred from a DMA-capable I/O or memory-mapped device

into system memory.

10 = Read transfer. Data is transferred from system memory to a DMA-capable I/O or

memory-mapped device.

11 = Reserved.

ELANSC520 Datasheet(PDF) 187 Page - Advanced Micro Devices

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