ELANSC520 datasheet(185/440 Pages) AMD

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GP DMA Controller Registers

Élan™SC520 Microcontroller Register Set Manual

11-53

Slave Software DRQ(n) Request (SLDMASWREQ)

Direct-Mapped

I/O Address 0009h

This register is used to initiate a software DMA request for one of Channels 0–3.

Bit Definitions

Programming Notes

Bit

Reserved

REQDMA

REQSEL[1–0]

Reset

00000

R/W

RSV

Bit

Name

Function

7–3

Reserved

This bit field should be written to 0 for normal system operation.

REQDMA

Software DMA Request

0 = Clear the request bit for the channel selected by the REQSEL bit field.

1 = Set the request bit for the channel selected by the REQSEL bit field.

The request bit is cleared internally after the corresponding channel has reached the end of

its transfer count.

1–0

REQSEL[1–0]

DMA Channel Select

This bit field selects the DMA channel that is to latch the REQDMA bit internally to assert or

deassert a DMA request via software:

00 = Select Channel 0 for internal DMA request per the REQDMA bit.

01 = Select Channel 1 for internal DMA request per the REQDMA bit.

10 = Select Channel 2 for internal DMA request per the REQDMA bit.

11 = Select Channel 3 for internal DMA request per the REQDMA bit.

ELANSC520 Datasheet(PDF) 185 Page - Advanced Micro Devices