ELANSC520 datasheet(186/440 Pages) AMD

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GP DMA Controller Registers

11-54

Élan™SC520 Microcontroller Register Set Manual

Slave DMA Channel 0–3 Mask (SLDMAMSK)

Direct-Mapped

I/O Address 000Ah

This register provides a mask or unmask capability for the DMA request signal to each of Channels 0–3.

Bit Definitions

Programming Notes

The same DMA channel masks can be controlled via DMA registers SLDMAMSK, SLDMAMSKRST (see

page 11-60), and SLDMAGENMSK (see page 11-61).

Before masking an active DMA channel, software must ensure that the DMA request is deasserted. Masking an

active channel while it is being granted might cause the system to hang.

Bit

Reserved

CHMASK

MSKSEL[1–0]

Reset

00000

R/W

RSV

Bit

Name

Function

7–3

Reserved

This bit field should be written to 0 for normal system operation.

CHMASK

DMA Channel Mask

0 = Clear the mask bit for the channel selected by the MSKSEL bit field.

1 = Set the mask bit for the channel selected by the MSKSEL bit field.

If the AINIT bit is 0 in the SLDMAMODE register (see page 11-55), the mask bit is set

internally when the corresponding channel reaches the end of its transfer count.

If the AINIT bit is 1, the mask bit remains clear when the transfer ends.

1–0

MSKSEL[1–0]

DMA Channel Mask Select

This bit field selects the DMA channel that is to latch the CHMASK bit internally to mask or

unmask the DMA request signal into the specified DMA channel:

00 = Mask or unmask DMA Channel 0 per the CHMASK bit.

01 = Mask or unmask DMA Channel 1 per the CHMASK bit.

10 = Mask or unmask DMA Channel 2 per the CHMASK bit.

11 = Mask or unmask DMA Channel 3 per the CHMASK bit.

ELANSC520 Datasheet(PDF) 186 Page - Advanced Micro Devices

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