ELANSC520 datasheet(182/440 Pages) AMD

182 / 440 page

GP DMA Controller Registers

11-50

Élan™SC520 Microcontroller Register Set Manual

Slave DMA Channel 0–3 Status (SLDMASTA)

Direct-Mapped

I/O Address 0008h

This register indicates the request status and terminal count status for Channels 0–3.

Bit Definitions

Programming Notes

Bits 3–0 of this register are reset when read. Any read from this register (SLDMASTA) clears bits 3–0.

Bit

DMAR3

DMAR2

DMAR1

DMAR0

TC3

TC2

TC1

TC0

Reset

????0000

R/W

RRRR

Bit

Name

Function

7DMAR3

Channel 3 DMA Request

0 = Channel 3 DMA request not pending

1 = Channel 3 DMA request pending

6DMAR2

Channel 2 DMA Request

0 = Channel 2 DMA request not pending

1 = Channel 2 DMA request pending

5DMAR1

Channel 1 DMA Request

0 = Channel 1 DMA request not pending

1 = Channel 1 DMA request pending

4DMAR0

Channel 0 DMA Request

0 = Channel 0 DMA request not pending

1 = Channel 0 DMA request pending

3TC3

Channel 3 Terminal Count

0 = Channel 3 terminal count not detected

1 = Channel 3 terminal count detected

2TC2

Channel 2 Terminal Count

0 = Channel 2 terminal count not detected

1 = Channel 2 terminal count detected

1TC1

Channel 1 Terminal Count

0 = Channel 1 terminal count not detected

1 = Channel 1 terminal count detected

0TC0

Channel 0 Terminal Count

0 = Channel 0 terminal count not detected

1 = Channel 0 terminal count detected

ELANSC520 Datasheet(PDF) 182 Page - Advanced Micro Devices

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