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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 31 of 141

Figure 5.5

Reset high at the end of POR

Figure 5.6

POR followed by Hardware Reset

5.3.2

IO3 / RESET# Input Initiated Hardware (Warm) Reset

The IO3 / RESET# signal functions as the RESET# input when CS# is high for more than tCS time or when Quad Mode is not

enabled CR1V[1]=0. The IO3 / RESET# input has an internal pull-up to VDD and may be left unconnected if Quad mode is not used.

The tCS delay after CS# goes high gives the memory or host system time to drive IO3 high after its use as a Quad mode I/O signal

while CS# was low. The internal pull-up to VDD will then hold IO3 / RESET# high until the host system begins driving IO3 / RESET#.

The IO3 / RESET# input is ignored while CS# remains high during tCS, to avoid an unintended Reset operation. If CS# is driven low

to start a new command, IO3 / RESET# is used as IO3.

When the device is not in quad mode or, when CS# is high, and IO3 / RESET# transitions from VIH to VIL for > tRP, following tCS, the

device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is

performed during POR. The hardware reset process requires a period of tRPH to complete. If the POR process did not complete

correctly for any reason during power-up (tPU), RESET# going low will initiate the full POR process instead of the hardware reset

process and will require tPU to complete the POR process.

The RESET command is independent of the state of IO3 / RESET#. If IO3 / RESET# is high or unconnected, and the RESET

instruction is issued, the device will perform software reset.

Additional IO3 RESET# notes:



IO3 / RESET# must be high for tRS following tPU or tRPH, before going low again to initiate a hardware reset.



When IO3 / RESET# is driven low for at least a minimum period of time (tRP), following tCS, the device terminates any

operation in progress, makes all outputs high impedance, and ignores all read/write commands for the duration of tRPH.

The device resets the interface to standby state.



If Quad mode and the IO3 / RESET# feature are enabled, the host system should not drive IO3 low during tCS, to avoid

driver contention on IO3. Immediately following commands that transfer data to the host in Quad mode, e.g. Quad I/O

Read, the memory drives IO3 / Reset high during tCS, to avoid an unintended Reset operation. Immediately following

commands that transfer data to the memory in Quad mode, e.g. Page Program, the host system should drive IO3 / Reset

high during tCS, to avoid an unintended Reset operation.



If Quad mode is not enabled, and if CS# is low at the time IO3 / RESET# is asserted low, CS# must return high during tRPH

before it can be asserted low again after tRH.

VCC

RESET#

CS#

If RESET# is high at tPU end

CS# may stay high or go low at tPU end

tPU

VCC

RESET#

CS#

tRS

tPU

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