S70FS01GS datasheet(14/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 14 of 141

Figure 3.2

SPI DDR Modes Supported

3.2

Command Protocol

All communication between the host system and FS-S Family memory devices is in the form of units called commands.

All commands begin with an 8-bit instruction that selects the type of information transfer or device operation to be performed.

Commands may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the

memory. All instruction, address, and data information is transferred sequentially between the host system and memory device.

Command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three

command phases:



instruction



address and instruction modifier (continuous read mode bits). For the S70FS01GS, do not enable the Continuous Read

Mode, this will cause bus contention between the two 512 Mb die.



data

Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI signal. Data may be

sent back to the host serially on the SO signal. This is referenced as a 1-1-1 command protocol for single bit width instruction, single

bit width address and modifier, single bit data.

Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble)

groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0,

IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O and 1-4-4 for Quad I/O command protocols.

The FS-S Family also supports a QPI mode in which all information is transferred in 4-bit width, including the instruction, address,

modifier, and data. This is referenced as a 4-4-4 command protocol.

Commands are structured as follows:



Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by the host

driving the Chip Select (CS#) signal low throughout a command.



The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.



Each command begins with an eight bit (byte) instruction. The instruction selects the type of information transfer or device

operation to be performed. The instruction transfers occur on SCK rising edges. However, some read commands are

modified by a prior read command, such that the instruction is implied from the earlier command. This is called Continuous

Read Mode. For the S70FS01GS, do not enable the Continuous Read Mode, this will cause bus contention between the

two 512 Mb die.



The instruction may be stand alone or may be followed by address bits to select a location within one of several address

spaces in the device. The instruction determines the address space used. The address may be either a 24 bit or a 32 bit,

byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in

DDR commands.

CPOL=0_CPHA=0_SCLK

CPOL=1_CPHA=1_SCLK

CS#

Transfer_Phase

Inst. 7

Inst. 0

A31

A30

DLP7

DLP0

Dummy / DLP

Address

Mode

Instruction

Read Data

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