S70FS01GS datasheet(90/141 Pages) CYPRESS

90 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 90 of 141

Figure 9.24

Dual I/O Read Command Sequence (3-Byte Address, BBh [CR2V[7]=0])

Note:

1. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these cycles to increase bus turn

around time between Mode bits from host and returning data from the memory. The Mode bits must not equal Axh, the Continuous Read Mode is not supported for the

S70FS01GS.

Figure 9.25

Dual I/O Read Command Sequence (4-Byte Address, BBh [CR2V[7]=1])

9.4.4

Quad I/O Read (QIOR EBh or 4QIOR ECh)

The instruction



EBh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or



EBh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or



ECh is followed by a 4-byte address (A31-A0)

The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3. It allows input of the address bits four bits per

serial SCK clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly from FS-S

Family devices. The QUAD bit of the Configuration Register must be set (CR1V[1]=1) to enable the Quad capability of FS-S Family

devices.

The maximum operating clock frequency for Quad I/O Read is 133MHz.

CS#

SCK

IO0

IO1

Phase

0 22

Instruction

Address

Mode

Dum

Data 1

Data 2

CS#

SCK

IO0

IO1

Phase

0 30

Instruction

Address

Mode

Dum

Data 1

Data 2

S70FS01GS Datasheet(PDF) 90 Page - Cypress Semiconductor

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