S70FS01GS datasheet(76/141 Pages) CYPRESS

76 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 76 of 141

9.1.5.2

Configuration

There are commands to read, write, and protect registers that control interface path width, interface timing, interface address length,

and some aspects of data protection.

9.1.6

Read Flash Array

Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from incrementally higher byte

addresses until the host ends the data transfer by driving CS# input High. If the byte address reaches the maximum address of the

memory array, the read will continue at address zero of the array.

Because the FS01GS is constructed from two FS512S devices stacked in a DDP, a sequential read access that reaches the

maximum address of a FS512S device, will continue at address zero of the same FS512S device. A sequential read at address

03FFFFFFh of an FS01GS will be followed by a read at 00000000h. A sequential read at address 07FFFFFFh of an FS01GS will be

followed by a read at 04000000h.

There are several different read commands to specify different access latency and data path widths. Double Data Rate (DDR)

commands also define the address & data bit relationship to both SCK edges:



The Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a single bit

per SCK falling edge on the SO signal. This command has zero latency between the address and the returning data but is

limited to a maximum SCK rate of 50MHz.



Other read commands have a latency period between the address and returning data but can operate at higher SCK

frequencies. The latency depends on a configuration register read latency value.



The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data returning a

single bit per SCK falling edge on the SO signal.



Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data returning two

bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.



Quad Double Data Rate read commands provide address four bits per every SCK edge with read data returning four bits of

data per every SCK edge on the IO0-IO3 signals.

9.1.7

Program Flash Array

Programming data requires two commands: Write Enable (WREN), and Page Program (PP). The Page Program command accepts

from 1 byte up to 256 or 512 consecutive bytes of data (page) to be programmed in one operation. Programming means that bits can

either be left at 1, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation.

9.1.8

Erase Flash Array

The Parameter Sector Erase, Sector Erase, or Bulk Erase commands set all the bits in a sector or the entire memory array to 1. A bit

needs to be first erased to 1 before programming can change it to a 0. While bits can be individually programmed from a 1 to 0,

erasing bits from 0 to 1 must be done on a sector-wide or array-wide (bulk) level. The Write Enable (WREN) command must precede

an erase command.

9.1.9

OTP, Block Protection, and Advanced Sector Protection

There are commands to read and program a separate One TIme Programmable (OTP) array for permanent data such as a serial

number. There are commands to control a contiguous group (block) of Flash memory array sectors that are protected from program

and erase operations.There are commands to control which individual Flash memory array sectors are protected from program and

erase operations. There is a mode to limit read access of the Flash array until a password is supplied.

9.1.10

Reset

There are commands to reset to the default conditions present after power on to the device. However, the software reset commands

do not affect the current state of the FREEZE or PPB Lock bits. In all other respects a software reset is the same as a hardware

reset.

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