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S70FS01GS Datasheet(PDF) 60 Page - Cypress Semiconductor |
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S70FS01GS Datasheet(HTML) 60 Page - Cypress Semiconductor |
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60 / 141 page ![]() S70FS01GS Document Number: 002-03833 Rev. *C Page 60 of 141 7.7.10 PPB Lock Register (PPBL) Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h), Read Any Register (RDAR 65h). PPBL does not have separate user programmable non-volatile bits, all defined bits are volatile read only status. The default state of the RFU bits is set by hardware. The default state of the PPBLOCK bit is defined by the ASP protection mode bits in ASPR[2:1]. There is no non-volatile version of the PPBL register. The PPBLOCK bit is used to protect the PPB bits. When PPBL[0] = 0, the PPB bits can not be programmed. In read password protection mode PPB Lock bit is also used to control the high order bits of address by forcing the address range to be limited to one sector where boot code is stored, until the read password is supplied. Table 7.21 PPB Lock Register (PPBL) Bits Field Name Function Type Default State Description 7 to 1 RFU Reserved Volatile 00h Reserved for Future Use 0 PPBLOCK Protect PPB Array Volatile Read Only ASPR[2:1] = 1xb = Persistent Protection Mode = 1 ASPR[2:1] = 01b = Password Protection Mode = 0 0 = PPB array protected 1 = PPB array may be programmed or erased. |
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