S70FS01GS datasheet(87/141 Pages) CYPRESS

87 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 87 of 141

Figure 9.21

Set Burst Length Command Sequence

9.4

Read Memory Array Commands

Read commands for the main Flash array provide many options for prior generation SPI compatibility or enhanced performance SPI:



Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate commands

(SDR).



Some SDR commands transfer address one bit per rising edge of SCK and return data 1bit of data per rising edge of SCK.

These are called Single width commands.



Some SDR commands transfer both address and data 2 or 4 bits per rising edge of SCK. These are called Dual I/O for 2

bit, Quad I/O, and QPI for 4 bit. QPI also transfers instructions 4 bits per rising edge.



Some commands transfer address and data on both the rising edge and falling edge of SCK. These are called Double Data

Rate (DDR) commands.



There are DDR commands for 4 bits of address or data per SCK edge. These are called Quad I/O DDR and QPI DDR for 4

bit per edge transfer.

All of these commands, except QPI Read, begin with an instruction code that is transferred one bit per SCK rising edge. QPI Read

transfers the instruction 4 bits per SCK rising edge.The instruction is followed by either a 3 or 4 byte address transferred at SDR or

DDR. Commands transferring address or data 2 or 4 bits per clock edge are called Multiple I/O (MIO) commands. For FS-S Family

devices at 256Mbits or higher density, the traditional SPI 3 byte addresses are unable to directly address all locations in the memory

array. Separate 4 Byte address read commands are provided for access to the entire address space. These devices may be

configured to take a 4 byte address from the host system with the traditional 3 byte address commands. The 4 byte address mode

for traditional commands is activated by setting the Address Length bit in configuration register 2 to “0”.

The Quad I/O and QPI commands provide a performance improvement option controlled by mode bits that are sent following the

address bits. The mode bits indicate whether the command following the end of the current read will be another read of the same

type, without an instruction at the beginning of the read. These mode bits give the option to eliminate the instruction cycles when

doing a series of Quad read accesses.

Some commands require delay cycles following the address or mode bits to allow time to access the memory array - read latency.

The delay or read latency cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory thus any data

provided by the host during these cycles is “don’t care” and the host may also leave the SI signal at high impedance during the

dummy cycles. When MIO commands are used the host must stop driving the IO signals (outputs are high impedance) before the

end of last dummy cycle. When DDR commands are used the host must not drive the I/O signals during any dummy cycle. The

number of dummy cycles varies with the SCK frequency or performance option selected via the Configuration Register 2

(CR2V[3:0]) Latency Code. Dummy cycles are measured from SCK falling edge to next SCK falling edge. SPI outputs are

traditionally driven to a new value on the falling edge of each SCK. Zero dummy cycles means the returning data is driven by the

memory on the same falling edge of SCK that the host stops driving address or mode bits.

The DDR commands may optionally have an 8 edge Data Learning Pattern (DLP) driven by the memory, on all data outputs, in the

dummy cycles immediately before the start of data. The DLP can help the host memory controller determine the phase shift from

SCK to data edges so that the memory controller can capture data at the center of the data eye.

When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides 1 or more dummy cycles should be

selected to allow additional time for the host to stop driving before the memory starts driving data, to minimize I/O driver conflict.

When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more dummy cycles should be selected to allow 1

cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP.

CS#

SCLK

Phase

Instruction

Input Data

S70FS01GS Datasheet(PDF) 87 Page - Cypress Semiconductor

S70FS01GS Datasheet(HTML) 87 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL