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S70FS01GS Datasheet(PDF) 82 Page - Cypress Semiconductor

Part # S70FS01GS
Description  1-Gbit (128 MByte), 1.8 V FS-S Flash
PDF  141 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S70FS01GS Datasheet(HTML) 82 Page - Cypress Semiconductor

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S70FS01GS
Document Number: 002-03833 Rev. *C
Page 82 of 141
This command is also supported in Quad All mode. In Quad AIl mode the instruction is shifted in on IO0-IO3, two clock cycles per
byte. The ECC read command is not supported for 0 dummy latency in Quad All mode.
Figure 9.13
ECCRD (19h), Quad All Mode, CR2[7] = 0, Command Sequence
Figure 9.14
ECCRD (19h), Quad All Mode, CR2[7] = 1, or 4ECCRD (18h) Command Sequence
9.3.5
Write VDLR (WVDLR 4Ah)
Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must be issued and
decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the Write
Enable Latch (WEL) to enable WVDLR operation.
The WVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WVDLR command is not
executed. As soon as CS# is driven to the logic high state, the WVDLR operation is initiated with no delays. The maximum clock
frequency for the PNVDLR command is 133 MHz.
Figure 9.15
Write VDLR (WVDLR) Command Sequence
CS
SCLK
IO0
IO1
IO2
IO3
Phase
4
0
20
4
0
4
0
4
0
4
0
4
0
5
1
21
5
1
5
1
5
1
5
1
5
1
6
2
22
6
2
6
2
6
2
6
2
6
2
7
3
23
7
3
7
3
7
3
7
3
7
3
Instruct.
Address
Dummy
D1
D2
D3
D4
CS
SCLK
IO0
IO1
IO2
IO3
Phase
4
0
28
4
0
4
0
4
0
4
0
4
0
5
1
29
5
1
5
1
5
1
5
1
5
1
6
2
30
6
2
6
2
6
2
6
2
6
2
7
3
31
7
3
7
3
7
3
7
3
7
3
Instruct.
Address
Dummy
D1
D2
D3
D4
CS#
SCK
SI
SO
Phase
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Instruction
Input Data



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