S70FS01GS datasheet(47/141 Pages) CYPRESS

47 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 47 of 141

7.7.1

Status Register-1

7.7.1.1

Status Register-1 Non-Volatile (SR1NV)

Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h)

Status Register Write Non-volatile (SRWD_NV) SR1NV[7]

: Places the device in the Hardware Protected mode when this bit is set

to 1 and the WP# input is driven low. In this mode, the Write Registers (WRR) and Write Any Register (WRAR) commands (that

select status register-1 or configuration register-1) are ignored and not accepted for execution, effectively locking the state of the

Status Register-1 and Configuration Register-1 (SR1NV, SR1V, CR1NV, or CR1V) bits, by making the registers read-only. If WP# is

high, Status Register-1 and Configuration Register-1 may be changed by the WRR or WRAR commands. If SRWD_NV is 0, WP#

has no effect and Status Register-1 and Configuration Register-1 may be changed by the WRR or WRAR commands. WP# has no

effect on the writing of any other registers. The SRWD_NV bit has the same non-volatile endurance as the main Flash array. The

SRWD (SR1V[7]) bit serves only as a copy of the SRWD_NV bit to provide zero read latency.

Program Error Default (P_ERR_D) SR1NV[6]

: Provides the default state for the Programming Error Status in SR1V[6]. This bit is

not user programmable.

Erase Error (E_ERR) SR1V[5]

: Provides the default state for the Erase Error Status in SR1V[5]. This bit is not user programmable.

Block Protection (BP_NV2, BP_NV1, BP_NV0) SR1NV[4:2]

: These bits define the main Flash array area to be software-protected

against program and erase commands. The BP bits are selected as either volatile or non-volatile, depending on the state of the BP

non-volatile bit (BPNV_O) in the configuration register CR1NV[3]. When CR1NV[3]=0 the non-volatile version of the BP bits

(SR1NV[4:2]) are used to control Block Protection and the WRR command writes SR1NV[4:2] and updates SR1V[4:2] to the same

value. When CR1NV[3]=1 the volatile version of the BP bits (SR1V[4:2]) are used to control Block Protection and the WRR

command writes SR1V[4:2] and does not affect SR1NV[4:2]. When one or more of the BP bits is set to 1, the relevant memory area

is protected against program and erase. The Bulk Erase (BE) command can be executed only when the BP bits are cleared to 0’s.

See Section 8.3 Block Protection on page 63 for a description of how the BP bit values select the memory array area protected. The

non-volatile version of the BP bits have the same non-volatile endurance as the main Flash array.

Write Enable Latch Default (WEL_D) SR1NV[1]

: Provides the default state for the WEL Status in SR1V[1]. This bit is programmed

by Cypress and is not user programmable.

Write In Progress Default (WIP_D) SR1NV[0]

: Provides the default state for the WIP Status in SR1V[0]. This bit is programmed by

Cypress and is not user programmable.

Table 7.5

Status Register-1 Non-Volatile (SR1NV)

Bits

Field Name

Function

Type

Default State

Description

SRWD_NV

Status Register

Write Disable

Default

Non-Volatile

1 = Locks state of SRWD, BP, and configuration register-1 bits when

WP# is low by not executing WRR or WRAR commands that would

affect SR1NV, SR1V, CR1NV, or CR1V.

0 = No protection, even when WP# is low

P_ERR_D

Programming Error

Default

Non-Volatile

Read Only

Provides the default state for the Programming Error Status. Not user

programmable.

E_ERR_D

Erase Error

Default

Non-Volatile

Read Only

Provides the default state for the Erase Error Status. Not user

programmable.

BP_NV2

Block Protection

Non-Volatile

000b

Protects the selected range of sectors (Block) from Program or

Erase when the BP bits are configured as non-volatile

(CR1NV[3]=0). Programmed to 111b when BP bits are configured to

volatile (CR1NV[3]=1).- after which these bits are no longer user

programmable.

BP_NV1

BP_NV0

WEL_D

WEL Default

Non-Volatile

Read Only

Provides the default state for the WEL Status. Not user

programmable.

WIP_D

WIP Default

Non-Volatile

Read Only

Provides the default state for the WIP Status. Not user

programmable.

S70FS01GS Datasheet(PDF) 47 Page - Cypress Semiconductor

S70FS01GS Datasheet(HTML) 47 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL