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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 52 of 141

Freeze Protection (FREEZE) CR1V[0]

: The Freeze Bit, when set to 1, locks the current state of the Block Protection control bits

and OTP area:



BPNV_2-0 bits in the non-volatile Status Register 1 (SR1NV[4:2])



BP 2-0 bits in the volatile Status Register 1 (SR1V[4:2])



TBPROT_O, TBPARM_O, and BPNV_O bits in the non-volatile Configuration Register (CR1NV[53, 2])



TBPROT, TBPARM, and BPNV bits in the volatile Configuration Register (CR1V[5, 3, 2]) are indirectly protected in that they

are shadows of the related CR1NV OTP bits and are read only



the entire OTP memory space

Any attempt to change the above listed bits while FREEZE = 1 is prevented:



The WRR command does not affect the listed bits and no error status is set.



The WRAR command does not affect the listed bits and no error status is set.



The OTPP command, with an address within the OTP area, fails and the P-ERR status is set.

As long as the FREEZE bit remains cleared to logic 0 the Block Protection control bits and FREEZE are writable, and the OTP

address space is programmable.

Once the FREEZE bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to power-on cycle or a hardware

reset. Software reset will not affect the state of the FREEZE bit.

The CR1V[0] FREEZE bit is volatile and the default state of FREEZE after power-on comes from FREEZE_D in CR1NV[0]. The

FREEZE bit can be set in parallel with updating other values in CR1V by a single WRR or WRAR command.

The FREEZE bit does not prevent the WRR or WRAR commands from changing the SRWD_NV (SR1NV[7]), Quad_NV

(CR1NV[1]), or QUAD (CR1V[1]) bits.

7.7.4

Configuration Register 2

Configuration register 2 controls certain interface functions. The register bits can be read and changed using the Read Any Register

and Write Any Register commands. The non-volatile version of the register provides the ability to set the POR, hardware reset, or

software reset state of the controls. These configuration bits are OTP and may only have their default state changed to the opposite

value one time during system configuration. The volatile version of the register controls the feature behavior during normal

operation.

7.7.4.1

Configuration Register 2 Non-volatile (CR2NV)

Related Commands: Read Any Register (RDAR 65h), Write Any Register (WRAR 71h).

Table 7.10

Configuration Register 2 Non-volatile (CR2NV)

Bits

Field Name

Function

Type

Default

State

Description

AL_NV

Address Length

OTP

1= 4 byte address

0= 3 byte address

QA_NV

QPI

1= Enabled -- QPI (4-4-4) protocol in use

0= Disabled -- Legacy SPI protocols in use, instruction is always

serial on SI

IO3R_NV

IO3 Reset

1= Enabled -- IO3 is used as RESET# input when CS# is high or

Quad Mode is disabled CR1V[1]=1

0= Disabled -- IO3 has no alternate function, hardware reset is

disabled.

RFU

Reserved

Reserved For Future Use

RL_NV

Read Latency

0 to 15 latency (dummy) cycles following read address or continuous

mode bits.

Note that bit 3 has a default value of 1 and may be programmed one

time to 0 but cannot be returned to 1.

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