S70FS01GS datasheet(18/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 18 of 141

Figure 3.12

DDR Quad I/O Read in QPI Mode

Additional sequence diagrams, specific to each command, are provided in section 9. Commands on page 71

3.3

Interface States

This section describes the input and output signal levels as related to the SPI interface behavior.

Legend

– Z

= no driver - floating signal,

– HL

= Host driving VIL,

– HH = Host driving VIH,

– HV = either HL or HH,

– X

= HL or HH or Z,

– HT = toggling between HL and HH,

– ML = Memory driving VIL,

– MH = Memory driving VIH,

– MV = either ML or MH.

Table 3.1

Interface States Summary

Interface State

VDD

SCK

CS#

IO3 / RESET#

WP# / IO2

SO / IO1

SI / IO0

Power-Off

<VDD (low)

Low Power

Hardware Data Protection

<VDD (cut-off)

Power-On (Cold) Reset

≥VDD (min)

Hardware (Warm) Reset Non-Quad Mode

≥VDD (min)

Hardware (Warm) Reset Quad Mode

≥VDD (min)

Interface Standby

≥VDD (min)

Instruction Cycle

(Legacy SPI)

≥VDD (min)

Single Input Cycle

Host to Memory Transfer

≥VDD (min)

Single Latency (Dummy) Cycle

≥VDD (min)

Single Output Cycle

Memory to Host Transfer

≥VDD (min)

Dual Input Cycle

Host to Memory Transfer

≥VDD (min)

Dual Latency (Dummy) Cycle

≥VDD (min)

Dual Output Cycle

Memory to Host Transfer

≥VDD (min)

Quad Input Cycle

Host to Memory Transfer

≥VDD (min)

Quad Latency (Dummy) Cycle

≥VDD (min)

Quad Output Cycle

Memory to Host Transfer

≥VDD (min)

DDR Quad Input Cycle

Host to Memory Transfer

≥VDD (min)

DDR Latency (Dummy) Cycle

≥VDD (min)

MV or Z

DDR Quad Output Cycle

Memory to Host Transfer

≥VDD (min)

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

28 24 20 16 12 8 4 0 4 0

7 6 5 4 3 2 1 0 4 0 4 0

29 25 21 17 13 9 5 1 5 1

7 6 5 4 3 2 1 0 5 1 5 1

30 26 22 18 14 10 6 2 6 2

7 6 5 4 3 2 1 0 6 2 6 2

31 27 23 19 15 11 7 3 7 3

7 6 5 4 3 2 1 0 7 3 7 3

Instruct.

Address

Mode

Dummy

DLP

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