S70FS01GS datasheet(89/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 89 of 141

Figure 9.23

Fast Read (FAST_READ) Command Sequence (3-Byte Address, 0Bh [CR2V[7]=0)

Note:

1. A = MSB of address = 23 for CR2V[7]=0, or 31 for CR2V[7]=1 or command 0Ch

9.4.3

Dual I/O Read (DIOR BBh or 4DIOR BCh)

The instruction



BBh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or



BBh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or



BCh is followed by a 4-byte address (A31-A0)

The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). This command takes input of the

address and returns read data two bits per SCK rising edge. In some applications, the reduced address input and data output time

might allow for code execution in place (XIP) i.e. directly from the memory device.

The maximum operating clock frequency for Dual I/O Read is 133 MHz.

The Dual I/O Read command has continuous read mode bits that follow the address. For the S70FS01GS, do not enable the

Continuous Read Mode, this will cause bus contention between the two 512Mb die. The first Dual I/O Read command in a series

starts with the 8 bit instruction, followed by address, followed by four cycles of mode bits not equal to Axh, followed by an optional

latency period.

Variable latency may be added after the mode bits are shifted into SI & SO before data begins shifting out of IO0 & IO1. This latency

period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the dummy

cycles, the data value on SI & SO are “don’t care” and may be high impedance. The number of dummy cycles is determined by the

frequency of SCK. The latency is configured in CR2V[3:0].

Note that the four mode bit cycles are part of the device’s internal circuitry latency time to access the initial address after the last

address cycle that is clocked into IO0 (SI) & IO1 (SO).

It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out clock. At higher clock

speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. It is

allowed and may be helpful in preventing I/O signal contention, for the host system to turn off the I/O signal outputs (make them high

impedance) during the last two “don’t care” mode cycles or during any dummy cycles.

Following the latency period the memory content, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1

(SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK signal.

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.

CS#

SCK

Phase

7 6

3 2

0 A

6 5

3 2

1 0

Instruction

Address

Dummy Cycles

Data 1

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