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S70FS01GS Datasheet(PDF) 33 Page - Cypress Semiconductor |
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S70FS01GS Datasheet(HTML) 33 Page - Cypress Semiconductor |
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33 / 141 page ![]() S70FS01GS Document Number: 002-03833 Rev. *C Page 33 of 141 5.4 SDR AC Characteristics Notes: 1. Only applicable as a constraint for WRR or WRAR instruction when SRWD is set to a 1. 2. Full VDD range & CL=30 pF. 3. Full VDD range & CL=15 pF. 4. Output HI-Z is defined as the point where data is no longer driven. 5. tCS and tDIS require additional time when the Reset feature and Quad mode are enabled (CR2V[5]=1 and CR1V[1]=1). 6. Tentative AC parameters, subject to device characterization, as DDP has increased I/O capacitance that may modify values slightly. Table 5.4 AC Characteristics Symbol Parameter Min Max Unit FSCK, R SCK Clock Frequency for READ & 4READ instructions DC 50 MHz FSCK, C SCK Clock Frequency for the following dual and quad commands: QOR, 4QOR, DIOR, 4DIOR, QIOR, 4QIOR DC 133 MHz FSCK, D SCK Clock Frequency for the following DDR commands: QIOR, 4QIOR DC 80 MHz PSCK SCK Clock Period 1/ FSCK ∞ tWH, tCH Clock High Time 50% PSCK -5% ns tWL, tCL Clock Low Time 50% PSCK -5% ns tCRT, tCLCH Clock Rise Time (slew rate) 0.1 V/ns tCFT, tCHCL Clock Fall Time (slew rate) 0.1 V/ns tCS CS# High Time (Read Instructions) CS# High Time (Read Instructions when Reset feature and Quad mode are both enabled) CS# High Time (Program/Erase Instructions) 10 20 (5) 50 ns tCSS CS# Active Setup Time (relative to SCK) 2 ns tCSH CS# Active Hold Time (relative to SCK) 3 ns tSU Data in Setup Time 2 ns tHD Data in Hold Time 3 ns tV Clock Low to Output Valid 8 (2) 6 (3) ns tHO Output Hold Time 1 ns tDIS Output Disable Time (4) Output Disable Time (when Reset feature and Quad mode are both enabled) 8 20 (5) ns tWPS WP# Setup Time (1) 20 ns tWPH WP# Hold Time (1) 100 ns tDPD CS# High to Power-down Mode 3µs tRES CS# High to Standby Mode without Electronic Signature Read 30 µs |
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